IP Library Patent Application 14332687
Patent Application
App. No. 14/332,687

METHOD FOR FABRICATING A METAL-INSULATOR-METAL (MIM) CAPACITOR HAVING CAPACITOR DIELECTRIC LAYER FORMED BY ATOMIC LAYER DEPOSITION (ALD)

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Patent No.
US None
App. No.
14/332,687
Abstract

In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO 2 , HfO 2 , (Zr x , Hf 1-x )O 2 (0<x<1), (Zr y , Ti 1-y )O 2 (0<y<1), (Hf z , Ti 1-z )O 2 (0<z<1), (Zr k , Ti l , Hf m )O 2 (0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.

Claims (28)

1 . A semiconductor device including a first transistor of a logic section and a second transistor of a DRAM section, comprising:

a first gate electrode of the first transistor formed over a semiconductor substrate of the logic section;

a first impurity region of the first transistor formed in the semiconductor substrate of the logic section;

a second gate electrode of the second transistor formed over the semiconductor substrate of the DRAM section;

a second impurity region of the second transistor formed in the semiconductor substrate of the DRAM section;

a plug formed over the secondary impurity region;

a lower electrode of a capacitor formed over the plug and electrically connected to the second impurity region through the plug,

a dielectric film of the capacitor formed over the lower electrode; and

an upper electrode of the capacitor formed over the dielectric film,

wherein the plug is formed of a first metal film,

wherein the lower electrode is formed of a second metal film,

wherein the upper electrode is formed of a third metal film,

wherein refractory metal silicide layers are formed on the first gate, the second gate, the first impurity region and the second impurity region, respectively, and

wherein the dielectric film includes Zr and O.

2 . A semiconductor device according to claim 1 ,

wherein the dielectric film is formed by ALD (Atomic Layer Deposition) method.

3 . A semiconductor device according to claim 2 ,

wherein a thickness of the dielectric film is 5 to 15 nm.

4 . A semiconductor device according to claim 2 ,

wherein the refractory metal silicide layers formed on the first gate, the second gate, the first impurity region and the second impurity region are formed at the same step.

5 . A semiconductor device according to claim 4 ,

wherein the refractory metal silicide layers include cobalt silicide or nickel silicide.

6 . A semiconductor device according to claim 2 ,

wherein the lower electrode includes TiN.

7 . A semiconductor device according to claim 6 ,

wherein the plug includes tungsten.

8 . A semiconductor device according to claim 7 ,

wherein the upper electrode includes TiN.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2014
From: IIZUKA, TOSHIHIRO; YAMAMOTO, TOMOE; TODA, MAMI; YAMAMICHI, SHINTARO
To: NEC CORPORATION
Reel/Frame 033323/0624 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2014
From: NEC CORPORATION
To: NEC ELECTRONICS CORPORATION
Reel/Frame 033323/0763 →
CHANGE OF NAME Recorded Jul 16, 2014
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 033323/0877 →