Selective single-ended transmission for high speed serial links
View Patent ↗Embodiments of systems and methods for selective single-ended transmission for high speed serial links. In an embodiment, a method includes training a data link in a differential mode. The method may also include training the data link in a single-ended mode. Additionally, the method may include dynamically operating the data link in the single-ended mode or the differential mode according to a monitored performance characteristic of the data link.
1. A method, comprising:
training a differential data link, by a Basic Input/Output System (BIOS) of an Information Handling System (IHS), in a differential mode;
training the differential data link, by the BIOS, in a first single-ended mode;
training the differential data link, by the BIOS, in a second single-ended mode;
operating the differential data link in the first single-ended mode with a first set of optimization parameters;
monitoring, by the BIOS, a performance characteristic of the differential data link in the first single-ended mode;
after operating the differential data link in the first single-ended mode and in response to a determination by the BIOS that the performance characteristic of the differential data link in the first single-ended mode is below a threshold, operating the differential data link in the second single-ended mode with a second set of optimization parameters;
monitoring, by the BIOS, the performance characteristic of the differential data link in the second single-ended mode; and
after operating the differential data link in the second single-ended mode and in response to a determination by the BIOS that the performance characteristic of the differential data link in the second single-ended mode is below the threshold, operating the differential data link in the differential mode with a third set of optimization parameters.
2. The method of claim 1 , wherein training the differential data link in the first and second single-ended modes further comprises:
training, by the BIOS, the differential data link in the first single-ended mode over a first conductor of a differential pair; and
training, by the BIOS, the differential data link in the second single-ended mode over a second conductor of the differential pair.
3. The method of claim 1 , further comprising selectively operating the differential data link, by the BIOS, in the first single-ended mode or the second single-ended mode according to the monitored performance characteristic of the differential data link.
4. The method of claim 2 , further comprising disabling, by the BIOS, a transmission component associated with the second conductor in response to the differential data link being operated in the first single-ended mode, and disabling, by the BIOS, a transmission component associated with the first conductor in response to a determination that the differential data link is being operated in the second single-ended mode.
5. The method of claim 1 , wherein the first, second, and third optimization parameters comprise: power or attenuation settings, line impedance matching settings, and filter settings.
6. The method of claim 1 , wherein the training uses a test pattern that covers worst-case crosstalk, worst-case noise, or worst-case simultaneous switching.
7. The method of claim 1 , wherein the threshold indicates error-free operation.
8. An Information Handling System (IHS), comprising:
a processor; and
a Basic Input/Output System (BIOS) coupled to the processor, the BIOS having program instructions stored thereon that, upon execution by the processor, cause the IHS to:
train a differential data link in a differential mode;
train the differential data link in a first single-ended mode;
train the differential data link in a second single-ended mode;
operate the differential data link in the first single-ended mode with a first set of optimization parameters;
monitor a performance characteristic of the differential data link in the first single-ended mode;
after operating the differential data link in the first single-ended mode and in response to a determination that the performance characteristic of the differential data link in the first single-ended mode is below a threshold, operate the differential data link in the second single-ended mode with a second set of optimization parameters;
monitor the performance characteristic of the differential data link in the second single-ended mode; and
after operating the differential data link in the second single-ended mode and in response to a determination by the BIOS that the performance characteristic of the differential data link in the second single-ended mode is below the threshold, operate the differential data link in the differential mode with a third set of optimization parameters.
9. The IHS of claim 8 , wherein to train the differential data link in the first and second single-ended modes, the program instructions, upon execution, further cause the IHS to:
train the differential data link in the first single-ended mode over a first conductor of a differential pair; and
train the differential data link in the second single-ended mode over a second conductor of the differential pair.
10. The IHS of claim 8 , wherein the program instructions, upon execution, further cause the IHS to selectively operate the differential data link in the first single-ended mode or the second single-ended mode according to the monitored performance characteristic of the differential data link.
11. The IHS of claim 10 , wherein the program instructions, upon execution, further cause the IHS to disable a transmission component associated with the second conductor in response to the differential data link being operated in the first single-ended mode, and to disable a transmission component associated with the first conductor in response to a determination that the differential data link is being operated in the second single-ended mode.
12. The IHS of claim 8 , wherein the first, second, and third optimization parameters comprise: power or attenuation settings, line impedance matching settings, and filter settings.
13. The IHS of claim 8 , wherein the training uses a test pattern that covers worst-case crosstalk, worst-case noise, or worst-case simultaneous switching.
14. The IHS of claim 8 , wherein the threshold indicates error-free operation.
15. A computer storage device coupled to a processor of an Information Handling System (IHS), the computer storage device having program instructions stored thereon that, upon execution by the processor, cause the IHS to:
train a differential data link in a differential mode;
train the differential data link in a first single-ended mode;
train the differential data link in a second single-ended mode;
operate the differential data link in the first single-ended mode with a first set of optimization parameters;
monitor a performance characteristic of the differential data link in the first single-ended mode;
after operating the differential data link in the first single-ended mode and in response to a determination that the performance characteristic of the differential data link in the first single-ended mode is below a threshold, operate the differential data link in the second single-ended mode with a second set of optimization parameters;
monitor the performance characteristic of the differential data link in the second single-ended mode; and
after operating the differential data link in the second single-ended mode and in response to a determination by the BIOS that the performance characteristic of the differential data link in the second single-ended mode is below the threshold, operate the differential data link in the differential mode with a third set of optimization parameters.
16. The computer storage device of claim 15 , wherein to train the differential data link in the first and second single-ended modes, the program instructions, upon execution, further cause the IHS to:
train the differential data link in the first single-ended mode over a first conductor of a differential pair; and
train the differential data link in the second single-ended mode over a second conductor of the differential pair.
17. The computer storage device of claim 15 , wherein the program instructions, upon execution, further cause the IHS to selectively operate the differential data link in the first single-ended mode or the second single-ended mode according to the monitored performance characteristic of the differential data link.
18. The computer storage device of claim 17 , wherein the program instructions, upon execution, further cause the IHS to disable a transmission component associated with the second conductor in response to the differential data link being operated in the first single-ended mode, and to disable a transmission component associated with the first conductor in response to a determination that the differential data link is being operated in the second single-ended mode.
19. The computer storage device of claim 15 , wherein the first, second, and third optimization parameters comprise: power or attenuation settings, line impedance matching settings, and filter settings.
20. The computer storage device of claim 15 , wherein the training uses a test pattern that covers worst-case crosstalk, worst-case noise, or worst-case simultaneous switching.