Memory system with selective access to first and second memories
View Patent ↗A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.
1. A memory system comprising:
a first nonvolatile memory;
a second nonvolatile memory;
a first signal line electrically connected to the first nonvolatile memory;
a second signal line electrically connected to the second nonvolatile memory;
an interface configured to connect to the first signal line and the second signal line;
a power supply unit configured to supply power to the first nonvolatile memory and the second nonvolatile memory; and
a controller configured to control the first nonvolatile memory and the second nonvolatile memory by controlling the first signal line and the second signal line, wherein
when the controller accesses the first nonvolatile memory, a load capacity of the first non-volatile memory is increased and a load capacity of the second nonvolatile memory is reduced, while the power supply unit supplies power to the memory system, and
when the controller accesses the second nonvolatile memory, the load capacity of the first nonvolatile memory is reduced and the load capacity of the second nonvolatile memory is increased, while the supply unit supplies power to the memory system.
2. The memory system according to claim 1 , wherein
the controller controls the load capacity of the first nonvolatile memory to be increased and the load capacity of the second nonvolatile memory to be reduced by electrically disconnecting the second signal line, when the first nonvolatile memory is accessed, and
the controller controls the load capacity of the first nonvolatile memory to be reduced and the load capacity of the second nonvolatile memory to be increased by electrically disconnecting the first signal line, when the second nonvolatile memory is accessed.
3. The memory system according to claim 1 , comprising
a plurality of the first nonvolatile memories and a plurality of the second nonvolatile memories,
the first signal line is electrically connected to the plurality of the first nonvolatile memories respectively, and
the second signal line is electrically connected to the plurality of the second nonvolatile memories respectively.
4. The memory system according to claim 1 , the interface comprising a switch configured to switch connection of the first signal line and the second signal line.
5. A memory system comprising:
a controller;
a first nonvolatile memory in the memory system;
a second nonvolatile memory in the memory system;
a first signal line electrically connected to the first nonvolatile memory;
a second signal line electrically connected to the second nonvolatile memory;
an interface configured to connect to the first signal line and the second signal line; and
a power supply unit configured to supply power to the memory system which includes the first nonvolatile memory and the second nonvolatile memory, wherein
when the controller accesses the first nonvolatile memory, a load capacity of the first nonvolatile memory is increased, while the power supply unit supplies power to the memory system, and
when the controller accesses the second nonvolatile memory, the load capacity of the first nonvolatile memory is reduced, while the power supply unit supplies power to the memory system.
6. A memory system comprising:
a nonvolatile memory;
a pin for sending a control signal to the nonvolatile memory;
a signal line electrically connected to the nonvolatile memory and the pin;
an interface configured to selectively connect to the first signal line and the second signal line; and
a power supply unit configured to supply power to the nonvolatile memory; wherein
a load capacity of the nonvolatile memory is increased, when the nonvolatile memory is accessed, while the power supply unit supplies power to the memory device, and
the load capacity of the nonvolatile memory is reduced, when the nonvolatile memory is not accessed, while the power supply unit supplies power to the memory device.