IP Library Granted Patent US 9,007,714
Granted Patent B1
US 9,007,714 · App. 14/335,653 · Granted Apr 14, 2015

Data storage device comprising slew rate anti-windup compensation for microactuator

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Quick Facts
Patent No.
US 9,007,714
App. No.
14/335,653
Granted
Apr 14, 2015
Kind
B1
Abstract

A data storage device is disclosed comprising a disk, a head, and a microactuator configured to actuate the head over the disk. An input signal to a compensator is generated, wherein the compensator is configured to generate a microactuator control signal. A slew rate signal representing a slew rate of the microactuator control signal is generated and applied to a first saturator configured to generate a saturated slew rate signal. The input signal is adjusted based on the slew rate saturation signal, and the microactuator is controlled based on the microactuator control signal.

Claims (50)

1. A data storage device comprising:

a disk;

a head;

a microactuator configured to actuate the head over the disk; and

control circuitry configured to:

generate an input signal to a compensator, wherein the compensator is configured to generate a microactuator control signal;

generate a slew rate signal representing a slew rate of the microactuator control signal;

apply the slew rate signal to a first saturator configured to generate a saturated slew rate signal;

adjust the input signal based on the slew rate saturation signal; and

control the microactuator based on the microactuator control signal.

2. The data storage device as recited in claim 1 , wherein the control circuitry is further configured to adjust the input signal based on a difference signal representing a difference between the slew rate signal and the saturated slew rate signal.

3. The data storage device as recited in claim 2 , wherein the control circuitry is further configured to differentiate the microactuator control signal to generate the slew rate signal.

4. The data storage device as recited in claim 3 , wherein the control circuitry is further configured to:

integrate the difference signal; and

adjust the input signal based on the integrated difference.

5. The data storage device as recited in claim 3 , wherein when the control circuitry is further configured to:

integrate the saturated slew rate signal;

apply the integrated saturated slew rate signal to a second saturator configured to generate a saturated microactuator control signal; and

control the microactuator based on the saturated microactuator control signal.

6. The data storage device as recited in claim 5 , wherein the control circuitry is further configured to adjust the input signal based on the saturated microactuator control signal.

7. The data storage device as recited in claim 1 , wherein the control circuitry is further configured to:

apply the microactuator control signal to a second saturator configured to generate a saturated amplitude signal; and

generate the slew rate signal based on the saturated amplitude signal.

8. The data storage device as recited in claim 7 , wherein the control circuitry is further configured to adjust the input signal based on a difference signal representing a difference between the microactuator control signal and the saturated slew rate signal.

9. The data storage device as recited in claim 8 , wherein the control circuitry is further configured to:

process the difference signal with a model of the microactautor to generate a compensation signal; and

adjust the input signal based on the compensation signal.

10. A method of operating a data storage device, the method comprising:

generating an input signal to a compensator, wherein the compensator is configured to generate a microactuator control signal for a microactuator configured to actuate a head over a disk;

generating a slew rate signal representing a slew rate of the microactuator control signal;

applying the slew rate signal to a first saturator configured to generate a saturated slew rate signal;

adjusting the input signal based on the slew rate saturation signal; and

controlling the microactuator based on the microactuator control signal.

11. The method as recited in claim 10 , further comprising adjusting the input signal based on a difference signal representing a difference between the slew rate signal and the saturated slew rate signal.

12. The method as recited in claim 11 , further comprising differentiating the microactuator control signal to generate the slew rate signal.

13. The method as recited in claim 12 , further comprising:

integrating the difference signal; and

adjusting the input signal based on the integrated difference.

14. The method as recited in claim 12 , further comprising:

integrating the saturated slew rate signal;

applying the integrated saturated slew rate signal to a second saturator configured to generate a saturated microactuator control signal; and

controlling the microactuator based on the saturated microactuator control signal.

15. The method recited in claim 14 , further comprising adjusting the input signal based on the saturated microactuator control signal.

16. The method as recited in claim 10 , further comprising:

applying the microactuator control signal to a second saturator configured to generate a saturated amplitude signal; and

generating the slew rate signal based on the saturated amplitude signal.

17. The method as recited in claim 16 , further comprising adjusting the input signal based on a difference signal representing a difference between the microactuator control signal and the saturated slew rate signal.

18. The method as recited in claim 17 , further comprising:

processing the difference signal with a model of the microactautor to generate a compensation signal; and

adjusting the input signal based on the compensation signal.

Assignments (7)
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 038744 FRAME 0481 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0556 →
RELEASE OF SECURITY INTEREST Recorded Mar 5, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045501/0714 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038722/0229 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038744/0281 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038744/0481 →