Transconductance (gm) boosting transistor arrangement
View Patent ↗A circuit may increase input transconductance. An input stage may include a field effect transistor (FET) that has a gate, source, drain, and body terminal. An amplifier may generate an amplified version of the input voltage received that is applied to the body terminal of the FET. Application of the amplified version to the body terminal of the FET may increase the transconductance of the FET compared to what it would be in the same circuit without the amplified version being applied to the body terminal of the FET.
1. A circuit for increasing input transconductance comprising:
an input that receives an input voltage;
an input stage that receives the input voltage from the input, the input stage including a field effect transistor (FET) that is directly connected to the input voltage and that has a gate, source, drain, and body terminal; and
an amplifier that has an input connected to the input voltage and that generates an amplified version of the input voltage received at the input that is applied to the body terminal of the FET,
wherein application of the amplified version to the body terminal of the FET increases the transconductance of the FET compared to what it would be in the same circuit without the amplified version being applied to the body terminal of the FET.
2. The circuit of claim 1 wherein the amplifier includes the FET.
3. The circuit of claim 2 further comprising a resistance connected to the body of the FET.
4. The circuit of claim 3 wherein the gain of the amplifier is proportional to the resistance.
5. The circuit of claim 1 wherein the amplifier generates a non-inverted amplified version of the input voltage.
6. The circuit of claim 1 wherein the amplified version of the input voltage is applied to the body terminal of the FET directly.
7. The circuit of claim 1 wherein the amplified version of the input voltage is applied to the body terminal of the FET through a capacitance.
8. The circuit of claim 7 further comprising a DC bias generation circuit that sets the DC operating point of the body terminal.
9. The circuit of claim 1 further comprising a cascode transistor that increases the output resistance of the input stage.
10. The circuit of claim 9 further comprising an auxiliary amplifier that boosts the output resistance of the cascode transistor.
11. The circuit of claim 1 wherein the:
the input receives a differential input voltage;
the input stage receives the differential input voltage from the input and includes a differential pair of FET transistors, each of which has a gate, source, drain, and body terminal; and
the amplifier generates an amplified version of the differential input voltage received at the input that is applied to the body terminal of each of the FETs.
12. The circuit of claim 11 wherein the amplifier generates a differential amplified version of the differential input voltage, one component of which is applied to the body terminal of one of the FETs, the other component of which is applied to the body terminal of the other FET.
13. The circuit of claim 12 wherein the amplifier includes the FET transistors.
14. The circuit of claim 13 further comprising a resistance connected to the drain of each FET.
15. The circuit of claim 14 wherein:
the gain of the amplifier that generates one component of the differential amplified version of the differential input voltage that is applied to the body terminal of one FET is proportional to the resistance that is connected to the drain of that FET; and
the gain of the amplifier that generates the other component of the differential amplified version of the differential input voltage that is applied to the body terminal of the other FET is proportional to the resistance that is connected to the drain of that other FET.
16. The circuit of claim 11 wherein the amplifier generates a non-inverted amplified version of each component of the differential input voltage.
17. The circuit of claim 13 wherein:
the differential input voltage has a positive and a negative component;
one of the FETs in the input stage amplifies the positive component of the input voltage;
the other FET in the input stage amplifies the negative component of the input voltage;
the differential amplified version of the positive component is delivered to the body of the FET that amplifies the negative component of the input voltage; and
the differential amplified version of the negative component is delivered to the body of the FET that amplifies the positive component of the input voltage.
18. The circuit of claim 17 wherein:
the amplified version of the positive component is delivered directly to the body of the FET that amplifies the negative component of the input voltage; and
the amplified version of the negative component is delivered directly to the body of the FET that amplifies the positive component of the input voltage.
19. The circuit of claim 17 wherein:
the amplified version of the positive component is delivered through a capacitance to the body of the FET that amplifies the negative component of the input voltage; and
the amplified version of the negative component is delivered through a capacitance to the body of the FET that amplifies the positive component of the input voltage.
20. The circuit of claim 19 further comprising a DC bias generation circuit that sets the DC operating point of the body terminal of each FET.
21. The circuit of claim 11 further comprising a cascode transistor that increases the output resistance of the input stage.
22. The circuit of claim 21 further comprising an auxiliary amplifier that boosts the output resistance of the cascode transistor.