Reducing data transition rates between analog and digital chips
View Patent ↗Provided are methods and systems for reducing a transition rate in transmitting data between analog and digital chips in Sigma-Delta Modulator (SDM) based Digital to Analog Converters (DACs) and Analog to Digital Converters (ADCs) intended to be used in audio signal processing. An example method may comprise receiving, by a digital chip, SDM binary data, mapping the SDM binary data to transition binary codes, and transmitting the transition binary codes to an analog chip. The mapping can be carried out according to a principle that the more commonly used SDM binary data codes correspond to transition binary data codes that require that fewer transitions occur in the signals between the chips. The methods and systems described provide for lowering the power needed for carrying out the data transmission between digital and analog chips.
1. A method for reducing a transition rate in transmitting data between digital and analog chips, the method comprising:
receiving, by an interface, data from a data source on a first chip;
mapping, by the interface, the data to a transition binary code, the transition binary code comprising a series of 0s and 1s, wherein a number of transitions from a 0 to 1 and from 1 to 0 depends on a probability of a value of the data;
applying an XOR filter to every other bit of the data while mapping the data to the transition binary codes;
transmitting, by the interface, the transition binary code to a second chip; and
applying an XOR filter to every other bit of the transition binary code after transmitting to the second chip.
2. The method of claim 1 , wherein the data represents an audio data stream.
3. The method of claim 1 , wherein the data includes sigma-delta modulator binary data.
4. The method of claim 1 , wherein the transition binary code representing the data having a more probable value includes fewer transitions from 0 and 1 and from 1 to 0 than the transition binary code representing the data having a less probable value.
5. The method of claim 1 , wherein the transition binary code is a non-return-to-zero inverted format code.
6. The method of claim 1 , wherein the data is received by packets from multiple parallel channels.
7. The method of claim 6 , further comprising:
serializing, by the interface, the packets to serial data before mapping to the transition binary code; and
parallelizing, by the interface, the transition binary code to further packets after transmitting to the second chip.
8. The method of claim 6 , further comprising:
serializing, by the interface, the packets to serial data after mapping to the transition binary code; and
parallelizing, by the interface, the transition binary code to further packets after transmitting to the second chip.
9. The method of claim 1 , wherein the data includes pulse-density modulation binary data.
10. The method of claim 1 , wherein a length of the series of the transition binary code is 5 bits.
11. A system for reducing a transition rate in transmitting data between digital and analog chips, the system comprising:
an interface configured to:
receive data from a data source on a first chip;
map the data to a transition binary code, the transition binary code comprising a series of 0s and 1s, wherein a number of transitions from 0 to 1 and from 1 to 0 depends on a probability of a value of the data;
apply an XOR filter to every other bit of the data while mapping the data to the transition binary code; and
transmit the transition binary code to a second chip, the second chip being configured to apply an XOR filter to every other bit of the transition binary code after receiving the transition binary code from the interface.
12. The system of claim 11 , wherein the data represents an audio data stream.
13. The system of claim 11 , wherein the data includes sigma-delta modulator binary data.
14. The system of claim 11 , wherein the transition binary code representing the data having a more probable value contains less transitions from 0 and 1 and from 1 to 0 than the transition binary code representing the data having a less probable value.
15. The system of claim 11 , wherein the transition binary code is a non-return-to-zero inverted format code.
16. The system of claim 11 , wherein the data is received by packets from multiple parallel channels.
17. The system of claim 16 , wherein the interface is further configured to:
serialize the packets to the data before mapping to the transition binary code; and
parallelize the transition binary code to further packets while transmitting to the second chip.
18. The system of claim 11 , wherein the data includes a pulse-density modulation binary data.
19. A non-transitory processor-readable medium having embodied thereon a program being executable by at least one processor to perform a method for reducing a transition rate in transmitting data between digital and analog chips, the method comprising:
receiving data from a data source on a first chip;
mapping the data to a transition binary code, the transition binary code comprising a series of 0s and 1s, wherein a number of transitions from 0 to 1 and from 1 to 0 depends on a probability of a value of the data;
applying an XOR filter to every other bit of the data while mapping the data to the transition binary codes;
transmitting the transition binary code to a second chip; and
applying an XOR filter to every other bit of the transition binary code after transmitting to the second chip.
20. The non-transitory processor-readable medium of claim 19 , wherein the data represents an audio data stream.
21. The non-transitory processor-readable medium of claim 19 , wherein the data includes at least one of sigma-delta modulator binary data and pulse-density modulation binary data.