Systems and Methods for Self Test Circuit Security

1 . A semiconductor device, the device comprising:

a wafer upon which an overall circuit is implemented, wherein the overall circuit includes: a first cell, a second cell, an internal only pad, an external pad, a gate circuit, and a test circuit;

wherein the test circuit is coupled to an output of the second cell and an output of the gate circuit;

wherein the overall circuit is selectably operable in a test mode or a functional mode based upon data received via the external pad;

wherein a first input of the gate circuit is coupled to the internal only pad and a second input of the gate circuit is coupled to an output of the first cell, and wherein the gate circuit is configured such that:

the output of the gate circuit follows the output of the first cell when the internal only pad is asserted at a first level and the test mode of the overall circuit is selected; and

the output of the gate circuit is fixed regardless of the output of the first cell when the internal only pad is asserted at a second level and the test mode of the overall circuit is selected.

2 . The device of claim 1 , wherein the output of the gate circuit is configured to follow the output of the first cell when the functional mode of the overall circuit is selected.

3 . The device of claim 1 , the device further comprising:

a test system electrically coupled to the wafer, wherein the test system is operable to assert the internal only pad at the first level.

4 . The device of claim 3 , wherein the test system is further operable to assert the external pad such that the test mode of the overall circuit is selected.

5 . The device of claim 1 , the device further comprising:

a chip package encapsulating the wafer and including a plurality of pins, wherein the external pad is bonded to one of the plurality of pins, and wherein the internal only pad is inaccessible via the plurality of pins.

6 . The device of claim 1 , the device further comprising:

a chip package encapsulating the wafer, wherein the external pad is bonded to a contact on the chip package such that the external pad is electrically accessible external to the chip package, and wherein the internal only pad is tied to the second level internal to the chip package.

7 . The device of claim 6 , wherein the internal only pad is not controllable external to the chip package beyond a power source applied to the chip package.

8 . The device of claim 1 , wherein the overall circuit includes at least one scan chain, wherein the second cell is included in the scan chain, and wherein the first cell is not incorporated in any of the at least one scan chain.

9 . The device of claim 1 , wherein the device is deployed as part of a consumer electronic device.

10 . The device of claim 9 , wherein the consumer electronic device is selected from a group consisting of: a hard disk drive, and a communication device.

11 . The device of claim 1 , wherein the gate circuit comprises:

a NAND gate having a first input coupled to the internal only pad and a second input coupled to a test select output associated with the external pad, and providing a gate signal; and

an AND gate having a first input coupled to the gate signal and a second input coupled to the output of the first cell, and providing the output of the gate circuit.

12 . A method for deploying a semiconductor device, the method comprising:

providing the semiconductor device, the semiconductor device comprising:

a wafer upon which an overall circuit is implemented, wherein the overall circuit includes: a first cell, a second cell, an internal only pad, an external pad, a gate circuit, and a test circuit;

wherein the test circuit is coupled to an output of the second cell and an output of the gate circuit;

wherein the overall circuit is selectably operable in a test mode or a functional mode based upon data received via the external pad;

wherein a first input of the gate circuit is coupled to the internal only pad and a second input of the gate circuit is coupled to an output of the first cell, and wherein the gate circuit is configured such that:

the output of the gate circuit follows the output of the first cell when the internal only pad is asserted at a first level and the test mode of the overall circuit is selected; and

the output of the gate circuit is fixed regardless of the output of the first cell when the internal only pad is asserted at a second level and the test mode of the overall circuit is selected.

13 . The method of claim 12 , the method further comprising:

electrically connecting the wafer to a test system;

tying the internal only pad at the first level;

asserting the external pad by the test system to engage a test mode of the overall circuit; and

verifying the wafer using the test system.

14 . The method of claim 12 , the method further comprising:

tying the internal only pad at the second level; and

encapsulating the wafer in a chip package such that the internal only pad is inaccessible external to the chip package.

15 . The method of claim 14 , wherein encapsulating the wafer in the chip package includes:

bonding an external contact of the chip package to the external pad; and

bonding the internal only pad to an internal power rail of the chip package.

16 . The method of claim 15 , wherein the internal only pad is not controllable external to the chip package beyond a power source applied to the chip package.

17 . The method of claim 12 , wherein the gate circuit comprises:

a NAND gate having a first input coupled to the internal only pad and a second input coupled to a test select output associated with the external pad, and providing a gate signal; and

an AND gate having a first input coupled to the gate signal and a second input coupled to the output of the first cell, and providing the output of the gate circuit.

18 . The method of claim 12 , wherein the overall circuit includes at least one scan chain, wherein the second cell is included in the scan chain, and wherein the first cell is not incorporated in any of the at least one scan chain.

19 . A circuit design tool, the design tool comprising:

a processor operable of receiving a representation of an overall circuit, wherein the overall circuit includes a first cell, a second cell, a third cell, an internal only pad, an external pad, a gate circuit, and a test circuit; and wherein the processor is communicably coupled to a computer readable medium including instructions executable by the processor to:

receive an identification of the cell as a secured memory;

disconnect the secured memory from a scan chain in the overall circuit;

connect a scan output from the second cell upstream from the secured memory in the scan chain to a scan input of the third cell downstream from the secured memory in the scan chain;

connect the gate circuit to the secured memory such that a first input of the gate circuit is coupled to the internal only pad and a second input of the gate circuit is coupled to an output of the secured memory, and wherein the gate circuit is configured such that:

the output of the gate circuit follows the output of the secured memory when the internal only pad is asserted at a first level and the test mode of the overall circuit is selected; and

the output of the gate circuit is fixed regardless of the output of the secured memory when the internal only pad is asserted at a second level and the test mode of the overall circuit is selected.

20 . The circuit design tool of claim 1 , wherein the gate circuit comprises:

a NAND gate having a first input coupled to the internal only pad and a second input coupled to a test select output associated with the external pad, and providing a gate signal; and

an AND gate having a first input coupled to the gate signal and a second input coupled to the output of the first cell, and providing the output of the gate circuit.