Semiconductor device
Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion ( 2 ) formed on the upper surface of a semiconductor substrate ( 1 ), a passivation layer ( 3 ) so formed on the upper surface of the semiconductor substrate ( 1 ) as to overlap a part of the electrode pad portion ( 2 ) and having a first opening portion ( 3 a ) where the upper surface of the electrode pad portion ( 2 ) is exposed, a barrier metal layer ( 5 ) formed on the electrode pad portion ( 2 ), and a solder bump ( 6 ) formed on the barrier metal layer ( 5 ). The barrier metal layer ( 5 ) is formed such that an outer peripheral end ( 5 b ) lies within the first opening portion ( 3 a ) of the passivation layer ( 3 ) when viewed in plan.
1. A semiconductor chip comprising:
an electrode pad portion on a face of a substrate;
a first protection layer disposed on the face of the substrate and overlapping a peripheral portion of the electrode pad portion establishing a first opening through which a first top face portion of the electrode pad portion is exposed, the first protection layer disposed on the face of the substrate and overlapping part of the electrode pad portion;
an insulating protection layer covering a region on the first protection layer and a region on the electrode pad portion such that a second opening exposing a second top face portion of the electrode pad portion is formed, the second opening being within the first opening and the second top face portion being within the first top face portion of the electrode pad portion; and
a barrier metal layer disposed on the second top face portion of the electrode pad portion, the barrier metal layer further comprising a peripheral part of the barrier metal layer formed over the insulating protection layer such that an electrode pad side facing surface of the peripheral part of the barrier metal layer comprises a curved surface having a center of curvature only on the electrode pad side of the barrier metal layer as seen in a sectional view.
2. The semiconductor chip of claim 1 , wherein the barrier metal layer has a circumferential end part thereof formed inward of the first opening in the first protection layer as seen in a plan view.
3. The semiconductor chip of claim 1 , wherein the barrier metal layer has a circumferential end part thereof formed outward of the first opening in the first protection layer as seen in a plan view.
4. The semiconductor chip of claim 1 , further comprising a bump electrode bonded to the barrier metal layer so as to cover at least the top surface of the barrier metal layer.
5. The semiconductor chip of claim 1 , wherein the insulating protection layer comprises polyimide.
6. A semiconductor device comprising the semiconductor chip of claim 1 .
7. The semiconductor chip of claim 1 , wherein a step part is formed where the first protection layer overlaps the peripheral portion of the electrode pad portion.
8. A semiconductor chip comprising:
an electrode pad portion on a face of a substrate;
a first protection layer disposed on the face of the substrate and overlapping a peripheral portion of the electrode pad portion establishing a first opening through which a first top face portion of the electrode pad portion is exposed, the first protection layer disposed on the face of the substrate and overlapping part of the electrode pad portion;
an insulating protection layer covering a region on the first protection layer and a region on the electrode pad portion such that a second opening exposing a second top face portion of the electrode pad portion is formed, the second opening being within the first opening and the second top face portion being within the first top face portion of the electrode pad portion; and
a barrier metal layer disposed on the second top face portion of the electrode pad portion;
the barrier metal layer further comprising a peripheral part of the barrier metal layer formed over the insulating protection layer such that an electrode pad side facing surface of the peripheral part of the barrier metal layer comprises a continuously curving surface that abuts an inclined upper surface of the insulating protection layer such that the continuously curving surface and the inclined upper surface of the insulating protection layer both terminate at the first top face portion of the electrode pad portion as seen in a sectional view.
9. The semiconductor chip of claim 8 , wherein the barrier metal layer has a circumferential end part thereof formed inward of the first opening in the first protection layer as seen in a plan view.
10. The semiconductor chip of claim 8 , wherein the barrier metal layer has a circumferential end part thereof formed outward of the first opening in the first protection layer as seen in a plan view.
11. The semiconductor chip of claim 8 , further comprising a bump electrode bonded to the barrier metal layer so as to cover at least the top surface of the barrier metal layer.
12. The semiconductor chip of claim 8 , wherein the insulating protection layer comprises polyimide.
13. A semiconductor device comprising the semiconductor chip of claim 8 .
14. The semiconductor chip of claim 8 , wherein a step part is formed where the first protection layer overlaps the peripheral portion of the electrode pad portion.
15. A semiconductor device comprising:
a semiconductor chip comprising:
an electrode pad portion on a face of a substrate;
a first protection layer disposed on the face of the substrate and overlapping a peripheral portion of the electrode pad portion establishing a first opening through which a first top face portion of the electrode pad portion is exposed, the first protection layer disposed on the face of the substrate and overlapping part of the electrode pad portion;
an insulating protection layer covering a region on the first protection layer and a region on the electrode pad portion such that a second opening exposing a second top face portion of the electrode pad portion is formed, the second opening being within the first opening and the second top face portion being within the first top face portion of the electrode pad portion;
a barrier metal layer disposed on the second top face portion of the electrode pad portion; the barrier metal layer further comprising a peripheral part of the barrier metal layer formed over the insulating protection layer such that an electrode pad side facing surface of the peripheral part of the barrier metal layer comprises a continuously curving surface that abuts an inclined upper surface of the insulating protection layer such that the continuously curving surface and the inclined upper surface of the insulating protection layer both terminate at the first top face portion of the electrode pad portion as seen in a sectional view; and
a bump electrode bonded to the barrier metal layer so as to cover at least the top surface of the barrier metal layer;
a printed circuit board having on a face thereof a connection pad portion connected to the bump electrode; and
a resin sealing layer between the semiconductor chip and the printed circuit board.
16. The semiconductor device of claim 15 , wherein the barrier metal layer has a circumferential end part thereof formed inward of the first opening in the first protection layer as seen in a plan view.
17. The semiconductor device of claim 15 , wherein the barrier metal layer has a circumferential end part thereof formed outward of the first opening in the first protection layer as seen in a plan view.
18. The semiconductor device of claim 15 , wherein the insulating protection layer comprises polyimide.
19. The semiconductor device of claim 15 , wherein a step part is formed where the first protection layer overlaps the peripheral portion of the electrode pad portion.
20. A semiconductor chip comprising:
an electrode pad portion on a face of a substrate;
a first protection layer disposed on the face of the substrate and overlaps a peripheral portion of the electrode pad portion establishing a first opening through which a first top face portion of the electrode pad portion is exposed, the first protection layer disposed on the face of the substrate and overlapping part of the electrode pad portion, and wherein a step part is formed where the first protection layer overlaps the peripheral portion of the electrode pad portion;
an insulating protection layer covering a region on the first protection layer and a region on the electrode pad portion such that a second opening exposing a second top face portion of the electrode pad portion is formed, the second opening being within the first opening and the second top face portion being within the first top face portion of the electrode pad portion; and
a barrier metal layer disposed on the second top face portion of the electrode pad portion;
the barrier metal layer further comprising a peripheral part of the barrier metal layer formed over the insulating protection layer such that an electrode pad side facing surface of the peripheral part of the barrier metal layer comprises a continuously curving surface that abuts an inclined upper surface of the insulating protection layer such that the continuously curving surface and the inclined upper surface of the insulating protection layer both terminate at the first top face portion of the electrode pad portion as seen in a sectional view.
21. The semiconductor chip of claim 20 , wherein the barrier metal layer has a circumferential end part thereof formed inward of the first opening in the first protection layer as seen in a plan view.
22. The semiconductor chip of claim 20 , wherein the barrier metal layer has a circumferential end part thereof formed outward of the first opening in the first protection layer as seen in a plan view.
23. The semiconductor chip of claim 20 , wherein the insulating protection layer comprises polyimide.