High voltage transistor device with reduced characteristic on resistance
View Patent ↗Technologies are generally described for reduction of the characteristic on resistance for a transistor device. In some examples, a transistor device may include a source region, a drain region, an n-type epitaxial region between the source and drain regions, a p-type body region, and a deep p-type trench region formed below the body region. The trench region may be configured to charge compensate the n-type epitaxial region. In other examples, the characteristic on resistance may be reduced by replacing the silicon below the body region with lower resistance conductive material. A backside of a wafer that includes the transistor device may be thinned by using a support or carrier on the front side of the wafer to provide mechanical support, and etching trenches in both the substrate silicon and the epitaxial silicon located below the body region of the transistor device. The trenches may be subsequently filled with conductive material.
1. A semiconductor device, comprising:
a substrate having a top portion, a bottom portion, and a height;
a body region of a selected type, wherein the body region is configured in contact with the top portion of the substrate;
a source region configured in contact with the body region;
a trench region located below the body region in the bottom portion of the substrate, wherein:
sidewalls of the trench region are of the selected type,
the sidewalls of the trench region are located substantially along the height of the substrate, and
the trench region is located through one or more of the source region and the body region;
a neck section configured in contact with the source region and the trench region; and
a dielectric spacer located in the neck section, wherein the dielectric spacer is configured to reduce interaction between a carrier concentration of the source region and a carrier concentration of the sidewalls of the trench region.
2. The semiconductor device of claim 1 , wherein the selected type corresponds to either a p-type region or an n-type region.
3. The semiconductor device of claim 1 , further comprising one of an oxide compound and a nitride compound configured to seal the sidewalls of the trench region near the neck section.
4. The semiconductor device of claim 1 , wherein the trench region includes an air gap region that is configured to facilitate thermal expansion of the trench region.
5. The semiconductor device of claim 1 , wherein the semiconductor device includes one of: a vertical transistor device, a lateral transistor device, an integrated transistor device, a discrete field effect transistor (FET) device, a field effect transistor (FET) device, a trench FET device, a shielded FET device, a vertical metal-oxide semiconductor (VMOS) transistor device, or a vertical diffusion metal-oxide semiconductor (VDMOS) transistor device.
6. The semiconductor device of claim 1 , wherein the trench region comprises one of tungsten and tantalum.
7. The semiconductor device of claim 1 , further comprising an epitaxial layer having a top portion, the epitaxial layer configured in contact with the top portion of the substrate.
8. The semiconductor device of claim 7 , wherein the body region is further configured in contact with the top portion of the epitaxial layer.
9. The semiconductor device of claim 7 , further comprising:
a gate region configured to be in contact with the top portion of the epitaxial layer such that the gate region partially overlaps with the body region; and
a drain region configured to be in contact with a bottom portion of the epitaxial layer.
10. The semiconductor device of claim 7 , wherein the trench region is configured to be positioned through the epitaxial layer.
11. The semiconductor device of claim 1 , wherein a depth of the trench region is in a range from about 5 micrometers to about 50 micrometers and a width of the trench region is in a range from about 2 micrometers to about 8 micrometers.
12. A method to fabricate a semiconductor device, the method comprising:
forming a body region of a selected type and configured in contact with a top portion of a substrate, wherein the substrate has the top portion, a bottom portion, and a height;
forming a source region configured in contact with the body region;
forming a trench region located below the body region in the bottom portion of the substrate, wherein:
sidewalls of the trench region are of the selected type,
the sidewalls of the trench region are located substantially along the height of the substrate, and
the trench region is located through one or more of the source region and the body region;
forming a neck section configured in contact with the source region and the trench region; and
forming a dielectric spacer located in the neck section, wherein the dielectric spacer is configured to reduce interaction between a carrier concentration of the source region and a carrier concentration of the sidewalls of the trench region.
13. The method of claim 12 , wherein forming the trench region comprises:
employing deep reactive ion etching (DRIE) to form the trench region.
14. The method of claim 12 , wherein forming the neck section configured in contact with the source region and the trench region comprises:
including an air gap region within the trench region that is configured to facilitate thermal expansion; and
applying a boron-type polysilicon to the neck section such that the sidewalls of the trench region are coated by the boron-type polysilicon.
15. The method of claim 12 , wherein forming the neck section configured in contact with the source region and the trench region comprises:
using one or more of an oxide compound and/or a nitride compound to seal the neck section.
16. The method of claim 12 , wherein the trench region comprises one of:
coating the sidewalls of the trench region with a boron-type polysilicon material using chemical vapor deposition (CVD); and
epitaxially depositing a boron-type silicon material on the sidewalls.
17. The method of claim 12 , further comprising:
removing a polysilicon material from a top portion of a wafer comprising the substrate for a plurality of semiconductor devices; and
wherein forming the source region configured in contact with the body region includes coupling the source region to the body region through silicon etching nitride spacers in the sidewalls of the trench region.
18. The method of claim 12 , further comprising:
planarizing a top surface of a wafer with a dielectric material;
forming contacts for: the source region, a shield layer, and a gate region; wherein the shield layer is coupled to the source region and configured to be maintained at a ground potential;
reducing a thickness of the wafer; and
metalizing at least a portion of a bottom surface of the wafer, wherein the portion of the bottom surface of the wafer is associated with a drain region of the semiconductor device.