Signal receiver

1. A DDR signal receiver, comprising:

a first stage amplifier, comprising:

a first current source, configured to provide a first current having a current value;

a first pair of active input devices, each of the first pair of active input devices having a control node, a first conduction node and a second conduction node, one control node of the pair of active input devices receiving an input signal, the first conduction nodes connected and receiving the first current, one of the second conduction nodes serving as an output nodes, the first pair of active input devices outputting an output signal to a core circuit according to the current and the input signal; and

a first pair of resistors, each resistor having a resistance value and connected between one of the second conduction nodes and a power line; and

a second-stage amplifier, comprising:

a second current source, configured to provide a second current;

a second pair of active input devices, each of the second pair of active input devices having a control node, a first conduction node and a second conduction node, the first conduction nodes of the second pair of active input devices connected to each other, the control nodes of the second pair of active input devices connected to the first-stage output nodes, respectively; and

a second pair of resistors, each of the second pair of resistors having second resistance value and connected between one of the second conduction nodes of the second pair of active input devices and the power line;

wherein, a target voltage value is determined according to the resistance value and the current value, such that a voltage swing of the output signal is limited within the target voltage value, and an operating voltage of the core circuit is substantially equal to the target voltage value, one of the second conduction nodes of the second pair of active input devices outputs second output signal, and a product of the second resistance value and the second current value is substantially equal to the operating voltage, the signal receiver is formed in an integrated circuit, the integrated circuit comprises a plurality of core devices and a plurality of high-voltage tolerant devices, the high-voltage tolerant devices have a higher voltage tolerance compared to the core devices, the pair of active input devices are high-voltage tolerant devices, and the second pair of active input devices are core devices.

2. The signal receiver according to claim 1 , wherein the first-stage and second-stage amplifiers have first and second voltage gains, respectively, the second voltage gain is greater than the first voltage gain, and the first voltage gain is greater than 1.

3. The signal receiver according to claim 1 , wherein the power line is a low-power analog circuit line, the current source is connected between the pair of active input devices and a high-power analog circuit line, and a voltage difference between the high-power analog circuit line and the low-power analog circuit line is higher than the operating voltage.

4. The signal receiver according to claim 1 , wherein the other of the control nodes is coupled to a reference voltage.

5. The signal receiver according to claim 1 , wherein the other of the control nodes receives another input signal, and the two input signals form a differential signal.

6. The signal receiver according to claim 1 , wherein the current source comprises a high-voltage tolerant current mirror.

7. A signal receiver, comprising:

a first-stage amplifier, configured to receive an input signal, and to process the input signal according to a first voltage gain to provide a first output signal; and

a second-stage amplifier, configured to receive the first output signal, and to process the first output signal according to a second voltage gain to generate a second output signal to a core circuit;

wherein a voltage swing of the second output signal is not greater than a predetermined value; wherein, the second voltage gain is greater than the first voltage gain, and the first voltage gain is greater than 1; and the core circuit is powered by a high-power digital circuit line and a low-power digital circuit line, and the predetermined value is substantially equal to a voltage difference between the high-power digital circuit line and the low-power digital circuit line,

wherein each of the first-stage and second-stage amplifiers comprises:

a current source, configured to provide a current;

a pair of active input devices, each of the pair of active input devices having a control node, a first conduction node and a second conduction node, the control nodes of the pair of active input devices serving as two signal input nodes, the first conduction nodes connected to each other and receiving the current, the second conduction nodes serving as two signal output nodes; and

a pair of resistors, each of the pair of resistors having a resistance value and connected between one of the second conduction nodes and an analog circuit power line;

wherein, a product of a current value of the current and the resistance value determines the predetermined value.

8. The signal receiver according to claim 7 , wherein the first-stage amplifier receives another input signal, the input signal and the another input signal form a differential signal, a common-mode output voltage of the first-stage amplifier is substantially equal to an average voltage of the high-power digital circuit line and the low-power digital circuit line.

9. The signal receiver according to claim 7 , wherein the signal receiver is formed in an integrated circuit, the integrated circuit comprises a plurality of core devices and a plurality of high-voltage tolerant devices, the pair of active input devices in the first-stage amplifier are high-voltage tolerant devices, and the pair of active input devices in the second-stage amplifier are core devices.