System and method for correcting errors in data using a compound code
View Patent ↗Storage of digital data in non-volatile media such as NAND FLASH needs to take account of the errors in data retrieved from the memory. The error rate tends to increase with the number of write/erase cycles of a cell of memory and with the time that the data has been stored. To achieve a very low uncorrected bit error rate (UBER) a substantial amount of redundancy data needs to be stored for error correction purposes. A method and apparatus is disclosed where a first redundancy data is represented by a second redundancy data computed from the first redundancy data. The first redundancy data may not be stored and is reconstructed from the stored data using a same generation procedure as previously used. The reconstructed estimate of the first redundancy data is corrected by the second redundancy data, and is used to correct the underlying data.
1. An apparatus to correct data errors, comprising:
a processor configured to use an error correcting code (ECC); and
a memory configured to store data, the data including ECC data;
wherein the ECC is used by the processor to identify a number of error bits in the data read from the memory and to correct the identified error bits;
a counter that stores the number of identified error bits by using the ECC;
a first limit of error bits that can be corrected by using the ECC;
a second limit of error bits that can be identified by using the ECC but cannot be corrected by using the ECC;
wherein the processor is configured to invert the identified error bits identified by using the ECC when the ECC is unable to be used to correct the identified error bits; and
wherein the processor is further configured to invert the error bits identified by using the ECC when the number of identified error bits is more than the first limit and less than the second limit; and
subsequently, the ECC is used to correct the data with the inverted bits.
2. The apparatus according to claim 1 , wherein the second limit of the error bits is two times as large as the first limit of the error bits.
3. The apparatus according to claim 1 , wherein the apparatus using the ECC is configured to instruct the processor to identify and correct the error bits after the processor has inverted the identified error bits until the ECC is used to corrects the error bits, up to a predetermined number of attempts to correct the data.
4. The apparatus according to claim 1 , wherein the data stored in the memory is encoded to generate redundant data characterizing the data before the data is stored, the apparatus using the ECC configures the processor to employ the redundant data to identify and correct the error bits.
5. The apparatus according to claim 4 , wherein the redundant data comprises: a first redundant data and a second redundant data wherein the first redundant data is stored in the memory and is used to identify and correct error bits in the second redundant data, and the second redundant data is not stored and is used by the apparatus using the ECC to identify and correct the error bits.
6. The apparatus according to claim 5 , wherein the first redundant data comprises a BCH code and the second redundant data comprises a LDPC code.
7. An apparatus to correct data errors, comprising:
a processor configured to process data including computing first redundant data and first second redundant data; and
a memory that stores the data and the first redundant data;
wherein the first redundant data is used to identify and correct errors in second second redundant data computed from the data read from the memory and the corrected second second redundant data is used to correct errors in the data read from the memory.
8. The apparatus according to claim 7 , further comprising:
a detecting unit configured to detect error bits in the data; and
an inversion unit configured to invert detected error bits when a number of error bits exceeds a correction capability of the second second redundant data.
9. The apparatus according to claim 8 , wherein the detecting unit comprises:
a counter that stores a number of the error bits that the processor is unable to correct;
a first limit of error bits that can be corrected by the processor ; and
a second limit of error bits that can be identified by the processor but cannot be corrected, wherein the inversion unit is configured to invert the error bits identified when the number of error bits is more than the first limit and less than the second limit.
10. The apparatus according to claim 7 , wherein the first redundant data comprises a BCH code and the first second redundant data comprises a LDPC code.
11. An system to correct data errors, comprising:
a first processor configured to process data including computing first redundant data and first second redundant data;
an interface that transmits data including the first redundant data
a receiver that receives the transmitted data and the first redundant data; and
a second processor configured to process the received data and the received first redundant data to compute second second redundant data;
wherein the first redundant data is used to identify and correct errors in the second second redundant data computed from the received data and the corrected second second redundant data is used to correct errors in the received data.
12. The system of claim 11 , further comprising:
a counter that stores a number of error bits the second processor is unable to correct;
a first limit of error bits that the second processor can correct;
a second limit of error bits that the second processor can detect; and
an inversion unit configured to invert the error bits when the number of error bits is more than the first limit and less than the second limit.
13. The system according to claim 11 , wherein the first redundant data comprises a BCH code and the first second redundant data comprises a LDPC code.