Methods and systems for managing performance and power utilization of a processor employing a fully-multithreaded load threshold
View Patent ↗A method for managing performance and power utilization of a processor in an information handling system (IHS) employing a balanced fully-multithreaded load threshold is disclosed. The method includes providing a maximum current thread utilization (Umax) and a minimum current thread utilization (Umin) among all current thread utilizations of the processor and determining a current performance state (P state) of the processor. The method also includes increasing a current P state of the processor to a next P state of the processor towards a maximum P state (Pmax) of the processor when the current P state of the processor is between Umax and Umin and the current utilization rate of the processor is less than a first threshold utilization rate. The method further includes engaging the processor in a turbo mode when the current P state of the processor reaches the Pmax and the current utilization of the processor is greater than the first threshold utilization rate of the processor.
1. A method for managing performance and power utilization of a processor in an information handling system, comprising:
determining, at a first time, a first maximum thread utilization (Umax1) and a first minimum thread utilization (Umin1) among a plurality of thread utilizations of a processor;
determining whether a restriction criterion is met by determining whether a difference between Umax1 and Umin1 is greater than a threshold difference; and
restricting engagement of a turbo mode of the processor if the restriction criterion is met.
2. The method of claim 1 , further comprising determining, at a second time, a second maximum thread utilization (Umax2) and a second minimum thread utilization (Umin2) among a plurality of thread utilizations of the processor,
wherein determining whether the restriction criterion is met further comprises determining whether a difference between Umax2 and Umin2 is greater than the threshold difference.
3. The method of claim 1 , further comprising determining, at the first time, a first utilization of the processor,
wherein determining whether the restriction criterion is met further comprises determining whether the first utilization of the processor is less than a first threshold utilization of the processor.
4. The method of claim 3 , further comprising determining, at a second time, a second utilization of the processor,
wherein determining whether the restriction criterion is met further comprises determining whether the second utilization of the processor is less than a second threshold utilization of the processor.
5. The method of claim 4 , wherein the first threshold utilization is different from the second threshold utilization.
6. The method of claim 1 , further comprising determining, at the first time, a first performance state (P1) of the processor,
wherein determining whether the restriction criterion is met further comprises determining whether P1 is less than a maximum performance state (Pmax) of the processor.
7. The method of claim 6 , further comprising determining, at a second time, a second performance state (P2) of the processor,
wherein determining whether the restriction criterion is met further comprises determining whether P2 is less than Pmax.
8. A non-transitory computer readable medium comprising instructions which, when executed on a processor, cause the processor to:
determine, at a first time, a first maximum thread utilization (Umax1) and a first minimum thread utilization (Umin2) among a plurality of thread utilizations of a processor;
determine whether a restriction criterion is met by determining whether a difference between Umax1 and Umin1 is greater than a threshold difference; and
restrict engagement of a turbo mode of the processor if the restriction criterion is met.
9. The non-transitory computer readable medium of claim 8 , wherein:
the instructions, when executed, further cause the processor to determine, at a second time, a second maximum thread utilization (Umax2) and a second minimum thread utilization (Umin2) among a plurality of thread utilizations of the processor; and
determining whether the restriction criterion is met further comprises determining whether a difference between Umax2 and Umin2 is greater than the threshold difference.
10. The non-transitory computer readable medium of claim 8 , wherein:
the instructions, when executed, further cause the processor to determine, at the first time, a first utilization of the processor; and
determining whether the restriction criterion is met further comprises determining whether the first utilization of the processor is less than a first threshold utilization of the processor.
11. The non-transitory computer readable medium of claim 10 , wherein:
the instructions, when executed, further cause the processor to determine, at a second time, a second utilization of the processor; and
determining whether the restriction criterion is met further comprises determining whether the second utilization of the processor is less than a second threshold utilization of the processor.
12. The non-transitory computer readable medium of claim 11 , wherein the first threshold utilization is different from the second threshold utilization.
13. The non-transitory computer readable medium of claim 8 , wherein:
the instructions, when executed, further cause the processor to determine, at the first time, a first performance state (P1) of the processor; and
determining whether the restriction criterion is met further comprises determining whether P1 is less than a maximum performance state (Pmax) of the processor.
14. The non-transitory computer readable medium of claim 13 , wherein:
the instructions, when executed, further cause the processor to determine, at a second time, a second performance state (P2) of the processor; and
determining whether the restriction criterion is met further comprises determining whether P2 is less than Pmax.
15. An information handling system comprising:
a processor;
a memory coupled to the processor; and
instructions contained in the memory which, when executed on the processor, cause the processor to:
determine, at a first time, a first maximum thread utilization (Umax1) and a first minimum thread utilization (Umin1) among a plurality of thread utilizations of the processor;
determine whether a restriction criterion is met by determining whether a difference between Umax1 and Umin1 is greater than a threshold difference; and
restrict engagement of a turbo mode of the processor if the restriction criterion is met.
16. The information handling system of claim 15 , wherein:
the instructions, when executed, further cause the processor to determine, at a second time, a second maximum thread utilization (Umax2) and a second minimum thread utilization (Umin2) among a plurality of thread utilizations of the processor; and
determining whether the restriction criterion is met further comprises determining whether a difference between Umax2 and Umin2 is greater than the threshold difference.
17. The information handling system of claim 15 , wherein:
the instructions, when executed, further cause the processor to determine, at the first time, a first utilization of the processor: and
determining whether the restriction criterion is met further comprises determining whether the first utilization of the processor is less than a first threshold utilization of the processor.
18. The information handling system of claim 17 , wherein:
the instructions, when executed, further cause the processor to determine, at a second time, a second utilization of the processor; and
determining whether the restriction criterion is met further comprises determining whether the second utilization of the processor is less than a second threshold utilization of the processor.
19. The information handling system of claim 15 , wherein:
the instructions, when executed, further cause the processor to determine, at the first time, a first performance state (P1) of the processor; and
determining whether the restriction criterion is met further comprises determining whether P1 is less than a maximum performance state (Pmax) of the processor.
20. The information handling system of claim 19 , wherein the instructions, when executed, further cause the processor to determine, at a second time, a second performance state (P2) of the processor, wherein determining whether the restriction criterion is met further comprises determining whether P2 is less than Pmax.