Nonvolatile semiconductor memory device

1. A nonvolatile semiconductor memory device comprising:

a memory cell array having a plurality of memory cells arranged in a matrix, wherein each of the memory cells includes a nonvolatile semiconductor memory element;

a plurality of word lines placed in one-to-one correspondence with rows of the memory cell array and each connected in common to a plurality of memory cells arranged in a corresponding one of the rows;

a plurality of bit lines placed in one-to-one correspondence with columns of the memory cell array and each connected in common to a plurality of memory cells arranged in a corresponding one of the columns;

a plurality of source lines;

a reference bit line;

a reference source line;

at least one reference cell including first and second transistors serially connected between the reference bit line and the reference source line;

a reference word line connected to a gate of the first transistor of the reference cell; and

a reference driver circuit configured to control a gate voltage of the second transistor of the reference cell, wherein

the at least one reference cell includes a plurality of reference cells,

the reference word line includes a plurality of reference word lines corresponding to the plurality of reference cells,

each of the plurality of reference word lines is connected to the gate of the first transistor of a corresponding one of the reference cells, and

the second transistor of at least one reference cell of the plurality of reference cells is configured to have a different transistor size from the second transistor of any other reference cell.

2. The nonvolatile semiconductor memory device of claim 1 , wherein

each of the plurality of memory cells includes a third transistor connected to the semiconductor memory element of the memory cell, and

the third transistor of each of the plurality of memory cells is identical in gate oxide film thickness to at least either of the first and second transistors.

3. The nonvolatile semiconductor memory device of claim 1 , wherein

each of the plurality of memory cells includes a third transistor connected to the semiconductor memory element of the memory cell, and

the third transistor of each of the plurality of memory cells is identical in gate channel length and gate channel width to at least either of the first and second transistors.

4. The nonvolatile semiconductor memory device of claim 1 , further comprising:

a sense amplifier circuit configured to determine data stored in the plurality of memory cells; and

a column gate circuit configured to connect one of the plurality of bit lines to the sense amplifier circuit and also connect the reference bit line to the sense amplifier circuit.

5. The nonvolatile semiconductor memory device of claim 1 , wherein

a reference cell array including the reference cell is placed to be adjacent to the memory cell array in a direction identical to the column direction of the memory cell array.

6. The nonvolatile semiconductor memory device of claim 5 , wherein

the reference cell array includes two reference cell arrays, and

the two reference cell arrays are placed to sandwich the memory cell array.