IP Library Granted Patent US 9,299,746
Granted Patent B2
US 9,299,746 · App. 14/345,295 · Granted Mar 29, 2016

Select device for cross point memory structures

Inventors: Gilberto M. Ribeiro (Palo Alto, CA); Janice H. Nickel (Sunnyvale, CA)
Assignee: Hewlett-Packard Enterprise Development LP
H01L27/2463G11C13/003G11C13/0004G11C13/004G11C13/0007G11C13/0011G11C13/0069H01L29/88H01L45/16G11C2213/33G11C2213/72
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Quick Facts
Patent No.
US 9,299,746
App. No.
14/345,295
Granted
Mar 29, 2016
Kind
B2
Abstract

The present disclosure provides a memory cell that includes a resistive memory element disposed between a first conductor and a second conductor, the first conductor and the second conductor configured to activate the resistive memory element. The memory cell also includes a backward diode disposed in series with the memory element between the memory element and either the first conductor or the second conductor.

Claims (12)

1. A memory cell, comprising:

a resistive memory element disposed between a first conductor and a second conductor, the first conductor and the second conductor configured to activate the resistive memory element; and

a backward diode disposed in series with the memory element between the memory element and either the first conductor or the second conductor, wherein the backward diode has a threshold voltage that is less than a write voltage of the resistive memory element, but is greater than half a write voltage of the resistive memory element.

2. The memory cell of claim 1 , wherein the resistive memory element comprises at least one of a memristor, a Phase Change Material resistor, a conductive bridge resistor, and a transition metal oxide based resistor.

3. The memory cell of claim 1 , wherein the resistive memory element is configured to be read by applying a voltage across the first conductor and the second conductor that reverse biases the backward diode and is less than a threshold voltage of the backward diode.

4. The memory cell of claim 1 , wherein the resistive memory element is configured to be written by applying a voltage across the first conductor and the second conductor that is greater than a threshold voltage of the backward diode.

5. The memory cell of claim 1 , wherein the backward diode comprises amorphous silicon, microcrystalline silicon, or a combination thereof.

6. A method of forming a memory cell, comprising:

disposing a resistive memory element between two electrodes;

disposing a backward diode in series with the resistive memory element between two electrodes, wherein the backward diode is configured to exhibit a threshold voltage less than a magnitude of a write voltage and greater than approximately one half of the magnitude of the write voltage.

7. The method of claim 6 , wherein disposing the resistive memory element comprises forming a memristor.

8. The method of claim 6 , wherein disposing the backward diode comprises forming a backward diode comprising amorphous silicon, microcrystalline silicon, or a combination thereof, over the resistive memory element.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2014
From: RIBEIRO, GILBERTO M; NICKEL, JANICE H
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 032868/0440 →
Continuity (1)
Related Publication 20140313816A1 · Oct 23, 2014