IGBT and method of manufacturing the same
View Patent ↗An IGBT has an emitter region, a top body region that is formed below the emitter region, a floating region that is formed below the top body region, a bottom body region that is formed below the floating region, a trench, a gate insulating film that covers an inner face of the trench, and a gate electrode that is arranged inside the trench. When a distribution of a concentration of p-type impurities in the top body region and the floating region, which are located below the emitter region, is viewed along a thickness direction of a semiconductor substrate, the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region, and assumes a local minimum value at a predetermined depth in the floating region.
1. An IGBT that is equipped with a semiconductor substrate, the IGBT comprising:
an n-type emitter region that is formed in such a range as to be exposed to an upper face of the semiconductor substrate;
a p-type top body region that is formed below the emitter region;
an n-type floating region that is formed below the top body region and separated from the emitter region by the top body region;
a p-type bottom body region that is formed below the floating region and separated from the top body region by the floating region;
a trench that is formed in the upper face of the semiconductor substrate and penetrates the emitter region, the top body region, the floating region, and the bottom body region;
a gate insulating film that covers an inner face of the trench; and
a gate electrode that is arranged inside the trench, wherein
when a distribution of a concentration of p-type impurities in the top body region and the floating region, which are located below the emitter region, is viewed along a thickness direction of the semiconductor substrate, the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region, and reaches a local minimum value at a predetermined depth in the floating region.
2. The IGBT according to claim 1 , wherein
when a distribution of a concentration of n-type impurities in the floating region is viewed along the thickness direction of the semiconductor substrate, a local maximum value of the concentration of the n-type impurities does not exist in the floating region.
3. The IGBT according to claim 1 , wherein
the floating region is formed by an epitaxial layer.
4. The IGBT according to claim 1 , wherein
when a distribution of a concentration of p-type impurities in the bottom body region is viewed along the thickness direction of the semiconductor substrate, a local maximum value of the concentration of the p-type impurities exists in the bottom body region.
5. The IGBT according to claim 1 , wherein
a width of the floating region along the thickness direction of the semiconductor substrate is wider at a position in contact with the gate insulating film than at a position away from the gate insulating film.
6. The IGBT according to claim 1 , wherein
a lower end of the bottom body region is located lower at a position in contact with the gate insulating film than at a position away from the gate insulating film.