IP Library Granted Patent US 9,451,189
Granted Patent B2
US 9,451,189 · App. 14/348,727 · Granted Sep 20, 2016

Solid-state image sensor and camera system

Inventors: Hayato Wakabayashi (Tokyo, JP); Yosuke Ueno (Kanagawa, JP)
Assignee: Sony Corporation
H04N5/369H04N5/3575H04N5/374H04N5/378H04N5/3745
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,451,189
App. No.
14/348,727
Granted
Sep 20, 2016
Kind
B2
Abstract

There is provided a solid-state image sensor including a pixel array unit in which pixels are arrayed, the pixel including a photodiode converting an optical signal into an electrical signal, and a readout unit which reads out an analog image signal from the pixel to a signal line and processes the read out analog pixel signal in a unit of column. The readout unit includes a ΔΣ modulator which has a function to convert the analog pixel signal in to a digital signal, and an amplifier which is arranged on an input side of the ΔΣ modulator and amplifies the analog pixel signal read out to the signal line using a set gain to input the signal to the ΔΣ modulator.

Claims (77)

1. A solid-state image sensor comprising:

a pixel array unit in which pixels are arrayed, at least a given pixel of the pixels including a photodiode converting an optical signal into an electrical signal; and

a readout unit that reads out an analog pixel signal from the given pixel to a signal line and processes the read out analog pixel signal in a unit of column,

wherein the readout unit includes

a ΔΣ modulator that has a function to convert the analog pixel signal in to a digital signal; and

an amplifier that is arranged upstream of the ΔΣ modulator, variably sets its own gain, amplifies the analog pixel signal read out to the signal line using the set gain, and inputs the amplified signal to the ΔΣ modulator, and

wherein the amplifier variably sets its own gain based on an input amplitude of the analog pixel signal and performs amplification such that a full-scale input range of the ΔΣ modulator is constant.

2. The solid-state image sensor according to claim 1 ,

wherein the ΔΣ modulator has input part that performs level shift of the pixel signal amplified by the amplifier to input the signal to an integrator, and

wherein an amount of the level shift is set as a fixed value.

3. The solid-state image sensor according to claim 1 ,

wherein the ΔΣ modulator is formed as n-dimensional (n is a positive number including 1) modulator, the ΔΣ modulator including

at least one integrator having an inverter type integrator;

a quantizer that quantizes an output signal of the integrator as the last stage and outputs a digital signal, and

a digital analog converter that converts the digital signal by the quantizer into an analog signal and feeds back on an input side of the integrator, and

wherein the amplifier includes

an inverter type amplifier or differential amplifier that has the same configuration as the inverter type integrator of the integrator.

4. The solid-state image sensor according to claim 3 ,

wherein the integrator of the ΔΣ modulator includes

an input capacitance connected on an input terminal side of the inverter type integrator, and

a feedback capacitance connected between an output terminal and input terminal of the inverter type integrator, and

wherein the amplifier includes

an input capacitance connected on an input terminal side of the inverter type amplifier, and

a feedback capacitance connected between an output terminal and input terminal of the inverter type amplifier.

5. The solid-state image sensor according to claim 3 ,

wherein the integrator of the ΔΣ modulator includes

an input capacitance connected on an input terminal side of the inverter type integrator, and

a feedback capacitance connected between an output terminal and input terminal of the inverter type integrator, and

wherein the amplifier includes

an input capacitance connected on one of input terminal sides of the differential amplifier,

a feedback capacitance connected between an output terminal and one of the input terminals of the differential amplifier, and

a reference voltage generation part supplying a reference voltage that is generated using a size ratio equivalent to an element forming the inverter type integrator, to the other input terminal of the differential amplifier.

6. The solid-state image sensor according to claim 4 ,

wherein the amplifier changes a capacitance ratio between the input capacitance and the feedback capacitance, and can set the gain corresponding to an input amplitude of the analog pixel signal.

7. The solid-state image sensor according to claim 4 ,

wherein the amplifier includes a reset switch that resets potentials of the output terminal and input terminal of the amplifier to a predetermined potential.

8. The solid-state image sensor according to claim 7 ,

wherein the pixel includes a reset function resetting an electrical charge of floating diffusion, and

wherein the reset switch of the amplifier is maintained in a conducting state in parallel with a reset operation of the pixel and resets potentials of the output terminal and input terminal of the amplifier.

9. The solid-state image sensor according to claim 1 , wherein the readout unit includes a decimation filter circuit converting the digital signal of the ΔΣ modulator into multiple bits.

10. A camera system comprising:

the solid-state image sensor according to claim 1 ; and

an optical system forming a subject image on the solid-state image sensor.

11. The camera system according to claim 10 ,

wherein the ΔΣ modulator has input part that performs level shift of the pixel signal amplified by the amplifier to input the signal to an integrator, and

wherein an amount of the level shift is set as a fixed value.

12. The camera system according to claim 10 ,

wherein the ΔΣ modulator is formed as n-dimensional (n is a positive number including 1) modulator, the ΔΣ modulator including

at least one integrator having an inverter type integrator;

a quantizer that quantizes an output signal of the integrator as the last stage and outputs a digital signal, and

a digital analog converter that converts the digital signal by the quantizer into an analog signal and feeds back on an input side of the integrator, and

wherein the amplifier includes

an inverter type amplifier or differential amplifier that has the same configuration as the inverter type integrator of the integrator.

13. The camera system according to claim 12 ,

wherein the integrator of the ΔΣ modulator includes

an input capacitance connected on an input terminal side of the inverter type integrator, and

a feedback capacitance connected between an output terminal and input terminal of the inverter type integrator, and

wherein the amplifier includes

an input capacitance connected on an input terminal side of the inverter type amplifier, and

a feedback capacitance connected between an output terminal and input terminal of the inverter type amplifier.

14. The camera system according to claim 12 ,

wherein the integrator of the ΔΣ modulator includes

an input capacitance connected on an input terminal side of the inverter type integrator, and

a feedback capacitance connected between an output terminal and input terminal of the inverter type integrator, and

wherein the amplifier includes

an input capacitance connected on one of input terminal sides of the differential amplifier,

a feedback capacitance connected between an output terminal and one of the input terminals of the differential amplifier, and

a reference voltage generation part supplying a reference voltage that is generated using a size ratio equivalent to an element forming the inverter type integrator, to the other input terminal of the differential amplifier.

15. The camera system according to claim 13 ,

wherein the amplifier changes a capacitance ratio between the input capacitance and the feedback capacitance, and can set the gain corresponding to input amplitude of the analog pixel signal.

16. The camera system according to claim 13 ,

wherein the amplifier includes a reset switch that resets potentials of the output terminal and input terminal of the amplifier to a predetermined potential.

17. The camera system according to claim 16 ,

wherein the pixel includes a reset function resetting an electrical charge of floating diffusion, and

wherein the reset switch of the amplifier is maintained in a conducting state in parallel with a reset operation of the pixel and resets potentials of the output terminal and input terminal of the amplifier.

18. The camera system according to claim 10 ,

wherein the readout unit includes a decimation filter circuit converting the digital signal of the ΔΣ modulator into multiple bits.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE ZIP CODE FROM 246-0014 TO 243-0014 PREVIOUSLY RECORDED AT REEL: 039645 FRAME: 0019. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 13, 2016
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 040894/0926 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2016
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 039645/0019 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2014
From: WAKABAYASHI, HAYATO; UENO, YOSUKE
To: SONY CORPORATION
Reel/Frame 032563/0820 →
Priority Claims (1)
JP 2011-230676 · Oct 20, 2011 · national
Continuity (1)
Related Publication 20140293103A1 · Oct 2, 2014