IP Library Granted Patent US 8,890,735
Granted Patent B2
US 8,890,735 · App. 14/351,059 · Granted Nov 18, 2014

Multi-level sigma-delta ADC with reduced quantization levels

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Quick Facts
Patent No.
US 8,890,735
App. No.
14/351,059
Granted
Nov 18, 2014
Kind
B2
Abstract

A multi-level sigma-delta Analog to Digital converter provides multi-level outputs using a quantizer with reduced quantization levels. The converter comprises a direct path comprising a computation block, an analog integrator and the quantizer with reduced quantization levels. Further, the converter comprises a feedback path arranged to provide to the computation block a feedback analog signal. The direct path comprises a first amplification block having a gain factor which is the inverse of the gain factor of a second amplification block of the feedback path. The converter allows reduction of the complexity of the quantizer.

Claims (21)

1. A multi-level sigma-delta Analog-to-Digital converter comprising:

a direct path having an input terminal to receive an input analog signal and an output terminal to provide an output digital signal corresponding to said input analog signal, said direct path comprising:

a computation block arranged to receive a first analog signal representative of the input analog signal and to provide an analog computed signal;

a first order analog integrator having an input terminal operatively associated to the computation block to receive the analog computed signal and an output terminal to provide a third analog signal,

a quantizer having a respective input terminal operatively connected to the output terminal of the first order analog integrator and a respective output terminal operatively connected to the output terminal of the direct path;

a first amplification block interposed between said computational block and the input terminal of the quantizer; and

a digital integrator block interposed between the output terminal of the quantizer and the output terminal of the converter, the digital integrator block being configured so that an output digital sample present at the output terminal of the direct path is added back directly at the output terminal of the quantizer; and

a first feedback path arranged to provide to the computation block a feedback analog signal representative of a digital signal present at the output terminal of the quantizer, said computation block being arranged to subtract said feedback analog signal from the first analog signal so that the output digital sample present at the output terminal of the quantizer is subtracted from the first analog signal, said first feedback path comprising an amplification block having a respective gain factor, said first amplification block of the direct path having a respective gain factor which is the inverse of the gain factor of the amplification block of the first feedback path.

2. The converter of claim 1 , further comprising a second feedback path arranged to provide to the computation block a further feedback analog signal representative of the output digital signal present at the output terminal of the direct path, said computation block being arranged to subtract said further feedback analog signal from the first analog signal.

3. The converter of claim 2 , wherein the direct path comprises a further analog integrator having an input terminal operatively connected to said input terminal of the direct path and an output terminal operatively connected to the computation block to provide it the first analog signal representative of the input analog signal of the direct path.

4. The converter of claim 3 , wherein the direct path comprises a further computation block arranged to receive the input analog signal and to provide a further analog computed signal to the further analog integrator.

5. The converter of claim 4 , wherein the second feedback path is further arranged to provide the feedback analog signal to the further computation block, said further computation block being arranged to subtract said further feedback analog signal from the first analog signal.

6. The converter of claim 5 , wherein the direct path further comprises a second amplification block interposed between the further computation block and the computation block, said second amplification block having a respective gain factor.

7. The converter of claim 1 , wherein the first amplification block of the direct path is interposed between the computation block and the first order analog integrator.

8. The converter of claim 1 , wherein the first amplification block of the direct path is interposed between the first order analog integrator and the quantizer.

9. The converter of claim 6 , wherein the second amplification block of the direct path is interposed between the further computation block and the further analog integrator.

10. The converter of claim 6 , wherein the second amplification block of the direct path is interposed between the further analog integrator and the computation block.

11. The converter of claim 1 , wherein the first feedback path further comprises a Digital-to-Analog converter interposed between the output terminal of the quantizer and the amplification block.

12. The converter of claim 2 , wherein the second feedback path comprises a further Digital-to-Analog converter.

13. The converter of claim 4 , wherein the computation block and the further computation block are configured to change from positive to negative the sign of the feedback analog signals received from the feedback paths.

14. A digital audio device comprises the converter of claim 1 .

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 10, 2019
From: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
To: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
Reel/Frame 049149/0276 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2019
From: OPTIS CIRCUIT TECHNOLOGY, LLC,
To: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
Reel/Frame 048529/0510 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2019
From: ST-ERICSSON SA, EN LIQUIDATION
To: OPTIS CIRCUIT TECHNOLOGY, LLC,
Reel/Frame 048504/0519 →
STATUS CHANGE-ENTITY IN LIQUIDATION Recorded Feb 2, 2016
From: ST-ERICSSON SA
To: ST-ERICSSON SA, EN LIQUIDATION
Reel/Frame 037739/0493 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 10, 2014
From: PINNA, CARLO
To: ST-ERICSSON SA
Reel/Frame 032650/0089 →