MOS device assembly
View Patent ↗A MOS device assembly having at least two transistors, each transistor having a gate region. The dimensions of the gate region of the first transistor are different from the dimensions of the gate region of the second transistor. The transconductance of the MOS device assembly is substantially uniform when the gate regions of the first and second transistors are biased using the same voltage.
1. A MOS device assembly comprising:
at least a first transistor and a second transistor, each of said first and second transistors having a gate and a gate region;
wherein dimensions of the gate or gate region of the first transistor are different from dimensions of the gate or gate region of the second transistor; and
wherein the MOS device assembly is configured to produce a plurality of transconductance peaks over a range of gate voltages so that a sum of the transconductance peaks results in a quasi-plateau having transconductance peaks of magnitudes over the gate voltages when the gates or gate regions of the first and second transistors are biased using the same voltage.
2. A MOS device assembly according to claim 1 , wherein the gate or gate region of each of the first and second transistors comprises an oxide region over a semiconductor active region of the MOS device assembly and a poly gate formed on the oxide region.
3. A MOS device assembly according to claim 2 , wherein a thickness of the oxide region of each of the first and second transistors is different.
4. A MOS device assembly according to claim 2 , wherein a width of the poly gate of each of the first and second transistors is different.
5. A MOS device assembly according to claim 2 , wherein a length of the poly gate of each of the first and second transistors is different.
6. A MOS device assembly according to claim 2 , wherein a thickness of the oxide region, a length and a width of the poly gate of each of said first and second transistors are different.
7. A MOS device assembly according to claim 1 , wherein a threshold voltage of each of the first and second transistors is different.
8. A MOS device assembly according to claim 7 , wherein the threshold voltages of each of the first and second transistors are chosen such that the transconductance of the MOS device assembly is quasi-plateaued having transconductance peaks of magnitudes over the range of gate voltages.
9. A MOS device assembly according to claim 8 , wherein the transconductance of the device assembly is quasi-plateaued having transconductance peaks of magnitudes over at least 20% of the range of gate voltages.
10. A MOS device assembly according to claim 8 , wherein the transconductance of the device assembly is quasi-plateaued having transconductance peaks of magnitudes over a gate voltage range of at least 0.7 V.
11. A MOS device assembly according to claim 1 , wherein the MOS device assembly comprises a common gate structure, wherein the gates of each of the first and second transistors form part of the common gate structure.
12. A MOS device assembly according to claim 11 , wherein the common gate structure is rectangularly shaped.
13. A MOS device assembly according to claim 11 , wherein the common gate structure is substantially cross-shaped.
14. A MOS device assembly according to claim 1 , wherein all of the first and second transistors are arranged to be connected in parallel.
15. A MOS device assembly according to claim 1 , wherein all of the first and second transistors share a common source formed in a semiconductor active region of the device assembly.
16. A MOS device assembly according to claim 1 , wherein all of the first and second transistors are arranged next to each other.
17. A MOS device assembly according to claim 1 , wherein the gate of each of the first and second transistors is a discrete gate having a discrete poly gate.
18. A MOS device assembly according to claim 1 , wherein the MOS device assembly further includes four transistors.
19. A MOS device assembly comprising:
at least a first transistor and a second transistor, each of the first and second transistors having a gate and a gate region;
wherein dimensions of the gate or gate region of the first transistor are different from dimensions of the gate or gate region of the second transistor; and
wherein the MOS device assembly is configured to produce a plurality of transconductance peaks over a gate voltage range of at least 0.7 V so that a sum of the transconductance peaks results in a quasi-plateau having transconductance peaks of magnitudes over said gate voltage range when the gates or gate regions of the first and second transistors are biased using the same voltage.
20. A MOS device assembly comprising:
at least a first transistor and a second transistor, each of the first and second transistors having a gate and a gate region;
wherein dimensions of the gate or gate region of the first transistor are different from dimensions of the gate or gate region of the second transistor, such that, when the gates or gate regions of the first and second transistors are biased using the same voltage, a uniformity of a transconductance of the MOS device assembly having a plurality of transconductance peaks over a predetermined range of gate voltages is greater when compared with a transconductance of the first transistor or the second transistor of the MOS device assembly over said predetermined range of gate voltages.
21. A MOS device assembly according to claim 20 , wherein the uniformity of the transconductance of the MOS device assembly is greater when compared with the transconductance of each of said first and second transistors.
22. A MOS device assembly according to claim 20 , wherein said predetermined range is at least 0.7 V.
23. A MOS device assembly according to claim 20 , wherein the uniformity of the MOS device assembly is greater over a range of gate voltages between 1V and 2V.
24. A method of manufacturing a MOS device assembly having at least a first transistor and a second transistor, the method comprising:
forming a first gate and a first gate region of the first transistor, and
forming a second gate and a second gate region of the second transistor, wherein dimensions of the first gate or the first gate region of the first transistor are different from dimensions of the second gate or the second gate region of the second transistor, and wherein the MOS device assembly is configured to produce a plurality of transconductance peaks over a range of gate voltages so that a sum of the transconductance peaks results in a quasi-plateau having transconductance peaks of magnitudes over the gate voltages when the gates or gate regions of the first and second transistors are biased using the same voltage.
25. A method according to claim 24 , wherein the gate of each of the first and second transistors further includes an oxide region over a semiconductor active region of the device and a poly gate formed on the oxide region.
26. A method according to claim 25 , wherein each of the first gate and the second gate is formed by:
providing the semiconductor active region having a source and a drain;
providing a sacrificial thermal oxide region by using masking, well implantation and cleaning;
removing the sacrificial thermal oxide region by wet cleaning;
providing a thermal gate oxide region having an oxide thickness; and
providing a mask to cover the thermal gate oxide region of one of the first and second transistors to remove the thermal gate oxide region of the other one of the first and second transistors.
27. A method according to claim 26 , wherein the thermal oxide region of each of the first and second transistors is grown using furnace oxidation.
28. A method according to claim 26 , further comprising depositing the poly gate over the thermal gate oxide region.
29. A method according to claim 24 , wherein the device assembly is manufactured using a CMOS technique.
30. A method according to claim 24 , further comprising controlling the matching between the first and second transistors using a matching layout technique comprising quad coupling.
31. A method of forming a MOS device assembly having at least a first transistor and a second transistor, the method comprising:
forming a first gate and a first gate region of the first transistor, and
forming a second gate and a second gate region of the second transistor, wherein dimensions of the first gate or first gate region of the first transistor are different from dimensions of the second gate or second gate region of the second transistor, and
choosing the dimensions of the first gate or the first gate region and the dimensions of the second gate or the second gate region to produce a plurality of transconductance peaks over a range of gate voltages so that a sum of the transconductance peaks results in a quasi-plateau having transconductance peaks of magnitudes over the gate voltages when the gates or the gate regions of the first and second transistors are biased using the same voltage.