IP Library Granted Patent US 9,648,743
Granted Patent B2
US 9,648,743 · App. 14/365,965 · Granted May 9, 2017

Multilayer glass ceramic substrate with embedded resistor

Inventors: Yousuke Futamata (Tokyo, JP); Hisashi Kobuke (Tokyo, JP)
Assignee: SNAPTRACK, INC.
H05K1/167H05K1/0306H05K3/4629
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Quick Facts
Patent No.
US 9,648,743
App. No.
14/365,965
Granted
May 9, 2017
Kind
B2
Abstract

A multilayer glass ceramic substrate includes a number of insulating layers composed of glass ceramics. An embedded resistor is formed between the insulating layers. The resistor includes scattered microvoids and includes materials containing conductive powders and glass powders. First and second internal conductors are provided where a first end of the embedded resistor is connected to the first internal conductor and a second end of the embedded resistor is connected to the second internal conductor.

Claims (11)

1. A multilayer glass ceramic substrate comprising:

a plurality of insulating layers composed of glass ceramics;

an embedded resistor formed between the insulating layers, wherein the resistor includes scattered microvoids and is comprised of materials containing conductive powders and glass powders, wherein an average size of the scattered microvoids is 3 μm or less, and wherein the average size of the scattered microvoids is 0.92 μm or more; and

a first and a second internal conductor, wherein a first end of the embedded resistor is connected to the first internal conductor and a second end of the embedded resistor is connected to the second internal conductor;

wherein a softening point of glass powders used for the resistor is expressed by Tr 1 ;

wherein the softening point of glass powders used for the insulating layers is expressed by Tc 1 ;

wherein Tc 1-110 ≦Tr 1 ≦Tc 1 +70 in degrees Celsius; and

wherein 750° C.≦Tc 1 ≦800° C.

2. The multilayer glass ceramic substrate according to claim 1 , wherein the insulating layer comprises a crystallized glass having a diopside crystal, that contains SiO 2 , CaO, and MgO, as a main phase.

3. The multilayer glass ceramic substrate according to claim 1 , wherein the proportion of the microvoids in the resistor on a cross section of the resistor that is parallel to a laminating surface of the multilayer glass ceramic substrate is 20% or less.

4. The multilayer glass ceramic substrate according to claim 2 , wherein the proportion of the microvoids in the resistor on a cross section of the resistor that is parallel to a laminating surface of the multilayer glass ceramic substrate is 20% or less.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2017
From: EPCOS AG
To: SNAPTRACK, INC.
Reel/Frame 041608/0145 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2014
From: FUTAMATA, YOUSUKE; KOBUKE, HISASHI
To: EPCOS AG
Reel/Frame 033530/0460 →
Priority Claims (1)
JP 2011-276172 · Dec 16, 2011 · national
Continuity (1)
Related Publication 20140305685A1 · Oct 16, 2014