Modulated clock synchronizer

1. A signal synchronization circuit comprising:

at least one synchronizer comprising a number N of series connected clock delay elements, N being equal to or greater than unity the synchronizer being adapted to adapt an asynchronous signal originating from a first clock domain, to a second clock domain;

a clock signal generator arranged for generating a modulated clock signal adapted to clock the N clocked delay elements of the at least one synchronizer, wherein the clock generator is arranged to receive a clock signal and at least one operating value and to generate the modulated clock signal from said clock signal modified based on said operating value; and

a clock gate with an input and an output, said input being arranged to receive the clock signal and said output being adapted to output the modulated clock signal from the clock signal generator, the clock gate being controlled by a control signal generated by the clock signal generator based on said operating value, wherein the operating value is tied to a desired increase in a synchronization time shift introduced by the synchronizer.

2. The circuit of claim 1 , wherein the operating value is tied to, preferably is representative of the number N of clock delay elements of the synchronizer, e.g., is equal to N.

3. The circuit of claim 1 , wherein the operating value is tied to at least one of a manufacturing process, operation voltage or temperature condition of the synchronizer.

4. The circuit of claim 1 , wherein the synchronizer comprises a clock gate with an input and an output, said input being arranged to receive the clock signal and said output being adapted to output a gated modulated clock signal from the clock signal generator, the clock gate being controlled by the modulated clock signal of the clock signal generator.

5. The circuit according to claim 1 , wherein the modulated clock signal is generated based further on a number M of clock delay elements which are necessary for the synchronizer to introduce a given time shift to the clock signal, M being greater than N, and wherein for a time sequence during which the clock signal comprises M rising edges, the modulated clock signal comprises N rising edges wherein the circuit further comprises a counter, said counter being adapted to update a counter value, and wherein, at each rising edge of the clock signal, if the counter value is below a given threshold, the edge of the modulated clock signal is caused to be low and the counter value is incremented by M−N, and else, the edge of the modulated clock signal is caused to be high and the counter value is decremented by N−1.

6. The circuit according to claim 1 , comprising at least two synchronizers, and wherein the modulated clock signal is adapted for clocking the clock delay element or elements of the synchronizers.

7. The circuit of claim 1 , wherein the synchronizer comprises the clock gate.

8. The circuit of claim 1 , wherein the clock signal generator comprises the clock gate.

9. A signal synchronization method comprising:

receiving a clock signal and at least one operating value;

generating a modulated clock signal from said clock signal modified based on said operating value, said modulated clock signal being adapted for clocking a number N of series connected clock delay elements of at least one synchronizer, N being equal to or greater than unity, the synchronizer being adapted to adapt an asynchronous signal originating from a first clock domain, to a second clock domain;

receiving, by an input of a clock gate, the clock signal; and

providing, by an output of the clock gate, the modulated clock signal to one of the clock delay elements, wherein the clock gate is controlled by a control signal based on the operating value,

wherein the operating value is tied to a desired increase in a synchronization time shift introduced by the synchronizer.

10. The method according to claim 9 , wherein the modulated clock signal is generated based further on a number M of clock delay elements which are necessary for the synchronizer to introduce a given time shift to the clock signal, M being greater than N, and wherein for a time sequence during which the clock signal comprises M rising edges, the modulated clock signal comprises N rising edges, and wherein, the method further comprises:

if a value of a counter is below a given threshold, the edge of the modulated clock signal is caused to be low and the counter value is incremented by M−N;

else, the edge of the modulated clock signal is caused to be high and the counter value is decremented by N−1 .

11. The method of claim 9 , wherein the operating value is tied to, preferably is representative of the number N of clock delay elements of the synchronizer, e.g., is equal to N.

12. The method of claim 9 , wherein the operating value is tied to at least one of a manufacturing process, operation voltage or temperature condition of the synchronizer.

13. A computer program product comprising a non-transitory computer readable medium having stored thereon computer program instructions loadable into a computing device, wherein the computer program instructions cause the computing device to:

receive a clock signal and at least one operating value;

generate a modulated clock signal from said clock signal modified based on said operating value, said modulated clock signal being adapted for clocking a number N of series connected clock delay elements of at least one synchronizer,

N being equal to or greater than unity, the synchronizer being adapted to adapt an asynchronous signal originating from a first clock domain, to a second clock domain;

receive, by an input of a clock gate, the clock signal; and

provide, by an output of the clock gate, the modulated clock signal to one of the clock delay elements, wherein the clock gate is controlled by a control signal based on the operating value,

wherein the operating value is tied to a desired increase in a synchronization time shift introduced by the synchronizer.

14. The computer program product according to claim 13 , wherein the modulated clock signal is generated based further on a number M of clock delay elements which are necessary for the synchronizer to introduce a given time shift to the clock signal, M being greater than N, and wherein for a time sequence during which the clock signal comprises M rising edges, the modulated clock signal comprises N rising edges, and wherein, the computer program instructions further causing the computing device to:

if a value of a counter is below a given threshold, the edge of the modulated clock signal is caused to be low and the counter value is incremented by M−N;

else, the edge of the modulated clock signal is caused to be high and the counter value is decremented by N−1.

15. The computer program product according to claim 13 , wherein the operating value is tied to, preferably is representative of the number N of clock delay elements of the synchronizer, e.g., is equal to N.

16. The computer program product according to claim 13 , wherein the operating value is tied to at least one of a manufacturing process, operation voltage or temperature condition of the synchronizer.