Wear leveling in a memory system
View Patent ↗Embodiments are disclosed for replacing one or more pages of a memory to level wear on the memory. In one embodiment, a system includes a page fault handling function and a memory address mapping function. Upon receipt of a page fault, the page fault handling function maps an evicted virtual memory address to a stressed page and maps a stressed virtual memory address to a free page using the memory address mapping function.
1. A device comprising:
a memory to:
receive a page fault indicative of an access to a virtual memory address unmapped in the memory;
in response to receiving the page fault,
map the unmapped virtual memory address to a stressed page of the memory; and
map a stressed virtual memory address to a free page of the memory, wherein the stressed page is determined based on one or more durability parameters, the durability parameters comprising an error correction parameter representing a frequency of detected and corrected errors in each of the pages of the memory.
2. The device according to claim 1 , the memory further to migrate data stored in an evicted page to a storage device, wherein the migrating recovers entries for a pool of free pages if the evicted page has been modified.
3. The device according to claim 1 , wherein the memory further to translate one or more memory addresses to physical memory addresses.
4. The device according to claim 1 , the memory further comprising a pool of free pages comprising a plurality of entries, wherein each entry in the pool of free pages is associated with a respective free page, a physical address of the free page, and a durability parameter of the free page.
5. The device according to claim 4 , wherein a head entry of the pool of free pages corresponds to the free page that is mapped to the stressed virtual memory address.
6. The device according to claim 4 , the memory further comprising an evicted page associated with an evicted virtual memory address, and wherein a tail entry of the pool of free pages corresponds to a physical address of the evicted page.
7. The device according to claim 5 , the memory further comprising a pool of marked pages comprising a plurality of entries, wherein each entry in the pool of marked pages is associated with a respective marked page, a physical address of the marked page, and a durability parameter of the marked page.
8. The device according to claim 7 , wherein a head entry of the pool of marked pages corresponds to the stressed page that is mapped to the unmapped virtual memory address.
9. The device according to claim 8 , the memory further to:
receive a durability parameter of the stressed page from a memory controller interface, and the stressed virtual memory address corresponding to the stressed page; and
generate the head entry in the pool of marked pages that is associated with the stressed page, a physical address of the stressed page, and the durability parameter of the stressed page.
10. The device according to claim 8 , the memory further to compare the durability parameter of the free page with the durability parameter of the stressed page.
11. The device according to claim 9 , wherein the respective durability parameters associated with the free page and the stressed page are selected from the group consisting of direct durability measurement, access counters, and error correction parameters.
12. A method comprising:
receiving, by a memory, a page fault indicative of an access to a virtual memory address unmapped in the memory;
in response to receiving the page fault, mapping the unmapped virtual memory address to a stressed page of the memory; and
providing instructions to migrate data stored in an evicted page to a storage device; and
mapping a stressed virtual memory address to a free page of the memory, wherein the stressed page is determined based on one or more durability parameters, the durability parameters comprising an error correction parameter representing a frequency of detected and corrected errors for the stressed page.
13. The method according to claim 12 , further comprising managing one or more free pages associated with a computing device using a pool of free pages wherein each entry in the pool of free pages is associated with a respective free page, a physical address of the free page, and a durability parameter of the free page.
14. The method according to claim 13 , wherein a head entry of the pool of free pages corresponds to the free page.
15. The method according to claim 13 , wherein an evicted page is associated with an evicted virtual memory address, and wherein a tail entry of the pool of free pages corresponds to a physical address of the evicted page.
16. The method according to claim 14 , further comprising managing wear leveling of one or more marked pages of the computing device using a pool of marked pages comprising a plurality of entries, wherein each entry in the pool of marked pages is associated with a respective marked page, a physical address of the marked page, and a durability parameter of the marked page.
17. The method according to claim 16 , wherein a head entry of the pool of marked pages corresponds to the stressed page that is mapped to the unmapped virtual memory address.
18. The method according to claim 17 , further comprising:
receiving a durability parameter of the stressed page and the stressed virtual memory address corresponding to the stressed page from a memory controller interface using a wear leveling module; and
generating the head entry of the pool of marked pages that is associated with the stressed page, a physical address of the stressed page, and the durability parameter of the stressed page.
19. The method according to claim 17 , further comprising comparing the durability parameter of the free page with the durability parameter of the stressed page.
20. The method according to claim 18 , wherein the respective durability parameters associated with the free page and the stressed page are at least one of direct durability measurement, access counters, or error correction parameters.