IP Library Granted Patent US 9,172,038
Granted Patent B2
US 9,172,038 · App. 14/371,331 · Granted Oct 27, 2015

Nonvolatile memory element and method of manufacturing the same

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Quick Facts
Patent No.
US 9,172,038
App. No.
14/371,331
Granted
Oct 27, 2015
Kind
B2
Abstract

A variable resistance layer between a first electrode and a second electrode includes: a first variable resistance layer contacting the first electrode; and a second variable resistance layer contacting the second electrode and having a lower degree of oxygen deficiency than the first variable resistance layer. A principal face of the first variable resistance layer which is close to the second variable resistance layer is flat. The second variable resistance layer is in contact with both the first variable resistance layer and the second electrode in a polygonal region including a vertex inward of an outline of the variable resistance layer and vertices along the outline when seen from a direction perpendicular to the principal face of the variable resistance layer, and is not in contact with at least one of the first variable resistance layer and the second electrode in a region outside the region inside the polygon.

Claims (19)

1. A nonvolatile memory element comprising:

a first electrode;

a second electrode; and

a variable resistance layer between the first electrode and the second electrode and having a resistance value that reversibly changes according to an electrical signal applied between the first electrode and the second electrode,

wherein the variable resistance layer includes a first variable resistance layer and a second variable resistance layer, the first variable resistance layer comprising a first metal oxide and contacting the first electrode, the second variable resistance layer comprising a second metal oxide and contacting the second electrode, the second metal oxide having a degree of oxygen deficiency lower than the degree of oxygen deficiency of the first metal oxide,

a principal face of the first variable resistance layer which is close to the second variable resistance layer is flat, and

the second variable resistance layer is in contact with both the first variable resistance layer and the second electrode in an interior region of a polygon including a single first vertex located inward of an outline of the variable resistance layer and plural second vertices located along the outline of the variable resistance layer when seen from a direction perpendicular to the principal face of the variable resistance layer, and is not in contact with at least one of the first variable resistance layer and the second electrode in a region outside the interior region of the polygon.

2. The nonvolatile memory element according to claim 1 ,

wherein an interior angle of the first vertex of the polygon is greater than 0 degrees and less than or equal to 90 degrees, or greater than or equal to 270 degrees and less than 360 degrees.

3. The nonvolatile memory element according to claim 1 ,

wherein a protective layer is provided between the first variable resistance layer and the second variable resistance layer, in the region outside the interior region of the polygon.

4. The nonvolatile memory element according to claim 1 ,

wherein a protective layer is provided between the second variable resistance layer and the second electrode, in the region outside the interior region of the polygon.

5. The nonvolatile memory element according to claim 1 ,

wherein the second electrode is provided only in the interior region of the polygon.

6. The nonvolatile memory element according to claim 1 ,

wherein each of the first metal oxide and the second metal oxide is a transition metal oxide or aluminum oxide.

7. The nonvolatile memory element according to claim 6 ,

wherein the transition metal oxide is any one of tantalum oxide, hafnium oxide, and zirconium oxide.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUSLY FILED APPLICATION NUMBERS 13/384239, 13/498734, 14/116681 AND 14/301144 PREVIOUSLY RECORDED ON REEL 034194 FRAME 0143. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 24, 2020
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 056788/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0870 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 034194/0143 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2014
From: HAYAKAWA, YUKIO; MIKAWA, TAKUMI
To: PANASONIC CORPORATION
Reel/Frame 033605/0413 →