IP Library Granted Patent US 9,397,563
Granted Patent B2
US 9,397,563 · App. 14/374,927 · Granted Jul 19, 2016

Driver circuit

Inventors: Seiichiro Kihara (Osaka, JP); Akio Nakajima (Osaka, JP)
Assignee: SHARP KABUSHIKI KAISHA
H02M3/157H02M1/08H03K17/063
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Quick Facts
Patent No.
US 9,397,563
App. No.
14/374,927
Granted
Jul 19, 2016
Kind
B2
Abstract

A driver circuit includes normally-on first and second transistors, a first control circuit for controlling the first transistor in response to a first control signal, a second control circuit for controlling the second transistor in response to a second control signal, a capacitor connected between first and second power supply nodes of the first control circuit, a power supply connected between third and fourth power supply nodes of the second control circuit, a switch element connected between first and fourth power supply nodes, and a third control circuit for turning the switch element on when an output voltage becomes about 0V.

Claims (45)

1. A driver circuit comprising:

a first transistor connected between a line of a first voltage and an output terminal;

a second transistor connected between said output terminal and a line of a second voltage lower than said first voltage;

a first control circuit including first and second power supply nodes, for supplying a voltage of said first power supply node to a control electrode of said first transistor to turn said first transistor on in response to setting of an input signal to a first logic level, and for supplying a voltage of said second power supply node to the control electrode of said first transistor to turn said first transistor off in response to setting of said input signal to a second logic level; and

a second control circuit including third and fourth power supply nodes, for supplying a voltage of said fourth power supply node to a control electrode of said second transistor to turn said second transistor off in response to setting of said input signal to said first logic level, and for supplying a voltage of said third power supply node to the control electrode of said second transistor to turn said second transistor on in response to setting of said input signal to said second logic level;

said first power supply node being connected to said output terminal,

said third power supply node receiving said second voltage,

said fourth power supply node receiving a third voltage lower than said second voltage,

said driver circuit further comprising:

a capacitor connected between said first and second power supply nodes;

a switch element connected between said second and fourth power supply nodes; and

a third control circuit for turning said switch element on to charge said capacitor in response to a decrease in a voltage corresponding to a difference between a voltage of said output terminal and said second voltage to a level lower than a predetermined voltage.

2. The driver circuit according to claim 1 , wherein

each of said first and second transistors is a normally-on transistor.

3. The driver circuit according to claim 2 , wherein

said normally-on transistor is an n channel FET made of a wide band gap semiconductor.

4. The driver circuit according to claim 1 , wherein

said switch element is an n channel MOSFET.

5. The driver circuit according to claim 1 , wherein

said third control circuit turns said switch element on when the voltage corresponding to the difference between the voltage of said output terminal and said second voltage decreases to a level lower than said predetermined voltage, and also when said input signal is at said second logic level.

6. The driver circuit according to claim 1 , wherein

said third voltage is set to a voltage allowing reverse conduction operation of said first or second transistor when said first or second transistor is off.

7. The driver circuit according to claim 6 , wherein

said third voltage is set such that a reverse conduction rising voltage of said first or second transistor is within a range from −1.5V to −3.0V.

8. A driver circuit comprising:

a first transistor connected between a line of a first voltage and an output terminal;

a second transistor connected between said output terminal and a line of a second voltage lower than said first voltage;

a first control circuit including first and second power supply nodes, for supplying a voltage of said first power supply node to a control electrode of said first transistor to turn said first transistor on in response to setting of an input signal to a first logic level, and for supplying a voltage of said second power supply node to the control electrode of said first transistor to turn said first transistor off in response to setting of said input signal to a second logic level; and

a second control circuit including third and fourth power supply nodes, for supplying a voltage of said fourth power supply node to a control electrode of said second transistor to turn said second transistor off in response to setting of said input signal to said first logic level, and for supplying a voltage of said third power supply node to the control electrode of said second transistor to turn said second transistor on in response to setting of said input signal to said second logic level;

said third power supply node receiving a third voltage higher than said second voltage,

said fourth power supply node receiving a fourth voltage lower than said second voltage,

said driver circuit further comprising:

a diode having an anode receiving said third voltage and a cathode connected to said first power supply node;

a first capacitor connected between said first power supply node and said output terminal;

a second capacitor connected between said second power supply node and said output terminal;

a switch element connected between said second and fourth power supply nodes; and

a third control circuit for turning said switch element on to charge said second capacitor in response to a decrease in a voltage corresponding to a difference between a voltage of said output terminal and said second voltage to a level lower than a predetermined voltage.

9. The driver circuit according to claim 8 , wherein

each of said first and second transistors is a normally-off transistor.

10. The driver circuit according to claim 9 , wherein

said normally-off transistor is an n channel FET made of a wide band gap semiconductor.

11. The driver circuit according to claim 8 , wherein

said switch element is an n channel MOSFET.

12. The driver circuit according to claim 8 , wherein

said third control circuit turns said switch element on when the voltage corresponding to the difference between the voltage of said output terminal and said second voltage decreases to a level lower than said predetermined voltage, and also when said input signal is at said second logic level.

Assignments (2)
NUNC PRO TUNC ASSIGNMENT Recorded Oct 14, 2021
From: SHARP KABUSHIKI KAISHA
To: ROHM CO., LTD
Reel/Frame 057790/0545 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2014
From: KIHARA, SEIICHIRO; NAKAJIMA, AKIO
To: SHARP KABUSHIKI KAISHA
Reel/Frame 033402/0656 →
Priority Claims (1)
JP 2012-016493 · Jan 30, 2012 · national
Continuity (1)
Related Publication 20140375292A1 · Dec 25, 2014