IP Library Granted Patent US 9,292,029
Granted Patent B2
US 9,292,029 · App. 14/379,399 · Granted Mar 22, 2016

Low-noise reference voltages distribution circuit

Inventors: Germano Nicollini (Piacenza, IT); Andrea Barbieri (Casalpusterlengo, IT)
Assignee: ST-ERICSSON SA
G05F3/262G05F1/56G05F1/561G05F3/26H03H7/0161
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Quick Facts
Patent No.
US 9,292,029
App. No.
14/379,399
Granted
Mar 22, 2016
Kind
B2
Abstract

A low-noise reference voltages distribution circuit has a multi-output voltage-to-current converter configured to receive an input reference voltage and to provide a plurality of output reference currents to be converted into a plurality of local reference voltages by corresponding receiving circuits. The converter includes an input section, an output section and a low-pass filter. The input section generates a reference current based on the input reference voltage, and has a current mirror input transistor having a voltage controlled input terminal. The output section includes a plurality of current mirror output transistors outputting reference currents to the plurality of reference currents, respectively, and having a voltage controlled input terminal connected to a common input node. The low-pass filter has an input node connected to the voltage controlled input terminal of the current mirror input transistor and an output node connected to the common input node.

Claims (46)

1. A reference voltages distribution circuit comprising:

a multi-output voltage to current converter configured to receive an input reference voltage and to provide a plurality of output reference currents to be converted into a plurality of local reference voltages at corresponding receiving circuits connected to said reference voltages distribution circuit, the multi-output voltage to current converter including:

an input section configured to generate a reference current based on the input reference voltage, the input section comprising a current mirror input transistor having a voltage controlled input terminal;

an output section having

a plurality of current mirror output transistors each configured to provide a corresponding output reference current of the plurality of output reference currents, and

a common input node to which voltage controlled input terminals of the current mirror output transistors are respectively connected; and

a low-pass filter having an input node connected to the voltage controlled input terminal of the current mirror input transistor, and an output node connected to the common input node of the output section, said low pass filter including:

a first MOS transistor having a first terminal connected to the input node of the low-pass-filter, a second terminal connected to the output node of the low-pass filter, and a gate terminal; and

a biasing circuit of said first MOS transistor configured to apply a DC control voltage to said gate terminal of the first MOS transistor such that the first MOS transistor operates in a weak inversion or a sub-threshold region, wherein said control voltage causes a desired resistance value R between said first terminal and said second terminal of the first MOS transistor.

2. The reference voltages distribution circuit according to claim 1 , wherein said desired resistance value R is in the Giga-ohm range.

3. The reference voltages distribution circuit according to claim 1 , wherein the low-pass filter is an RC filter with a time constant having value R*C, where:

R is said desired resistance value between said first terminal and said second terminal of the first MOS transistor, and

C is a capacitance value greater than or equal to an equivalent input capacitance of the output section,

said time constant value R*C being selected such that to obtain a desired value for a cutoff frequency of the low-pass filter.

4. The reference voltages distribution circuit according to claim 3 , wherein each of the current mirror output transistors is a MOS transistor having a gate terminal connected to said common input node of said output section, said equivalent input capacitance of the output section being equal to a sum of gate capacitances of the current mirror output transistors.

5. The reference voltages distribution circuit according to claim 1 , wherein each of said current mirror output transistors has a terminal connected to the common node, and the low-pass filter further comprises a capacitor having a first end connected to the output node of said low-pass filter and a second end connected to said common node.

6. The reference voltages distribution circuit according to claim 1 , wherein the low-pass filter has a cutoff frequency not greater than 10 Hz.

7. The reference voltages distribution circuit according to claim 1 , wherein said biasing circuit comprises:

a first current generator;

a second current generator;

at least a second MOS transistor having a diode configuration, being connected between the first and the second current generator, and having a gate terminal connected to said gate terminal of the first MOS transistor and a source terminal connected to the input node of the low-pass-filter.

8. The reference voltages distribution circuit according to claim 7 , wherein said first and second current generators are configured to generate currents having a same current value, said current value being not greater than 1 μA.

9. The reference voltages distribution circuit according to claim 1 , wherein drains of the current mirror input transistor and of each of the plurality of current mirror output transistors are connected with sources of respective additional transistors in a cascode configuration.

10. The reference voltages distribution circuit according to claim 1 , wherein in said multi-output voltage to current converter, the input section, the low-pass filter and the output section are integrated on a same chip.

11. The reference voltages distribution circuit according to claim 1 ,

wherein the input section is a multi-stage CMOS amplifier comprising an input stage and an output stage, and

wherein said output stage comprises said current mirror input transistor.

12. The reference voltages distribution circuit according to claim 1 , wherein the input section is a two-stage CMOS amplifier.

13. A mixed signal integrated circuit comprising a reference voltages distribution circuit including a multi-output voltage to current converter configured to receive an input reference voltage and to provide a plurality of output reference currents to be converted into a plurality of local reference voltages at corresponding receiving circuits connected to said reference voltages distribution circuit, the multi-output voltage to current converter including:

an input section configured to generate a reference current based on the input reference voltage, the input section comprising a current mirror input transistor having a voltage controlled input terminal;

an output section having

a plurality of current mirror output transistors each configured to provide a corresponding output reference current of the plurality of output reference currents, and

a common input node to which voltage controlled input terminals of the current mirror output transistors are respectively connected; and

a low-pass filter having an input node connected to the voltage controlled input terminal of the current mirror input transistor, and an output node connected to the common input node of the output section, said low pass filter including:

a first MOS transistor having a first terminal connected to the input node of the low-pass-filter, a second terminal connected to the output node of the low-pass filter, and a gate terminal, and

a biasing circuit of said first MOS transistor configured to apply a DC control voltage to said gate terminal of the first MOS transistor such that the first MOS transistor operates in a weak inversion or a sub-threshold region, wherein said control voltage causes a desired resistance value R between said first terminal and said second terminal of the first MOS transistor.

14. A method to provide a plurality of local reference voltages to corresponding receiving circuits, the method comprising:

providing the plurality of local reference voltages to the corresponding receiving circuits using a reference voltages distribution circuit including a multi-output voltage to current converter configured to receive an input reference voltage and to provide a plurality of output reference currents to be converted into a plurality of local reference voltages at corresponding receiving circuits connected to said reference voltages distribution circuit,

wherein the multi-output voltage to current converter includes:

an input section configured to generate a reference current based on the input reference voltage, the input section comprising a current mirror input transistor having a voltage controlled input terminal;

an output section having

a plurality of current mirror output transistors each configured to provide a corresponding output reference current of the plurality of output reference currents, and

a common input node to which voltage controlled input terminals of the current mirror output transistors are respectively connected; and

a low-pass filter having an input node connected to the voltage controlled input terminal of the current mirror input transistor, and an output node connected to the common input node of the output section, said low pass filter including:

a first MOS transistor having a first terminal connected to the input node of the low-pass-filter, a second terminal connected to the output node of the low-pass filter, and a gate terminal, and

a biasing circuit of said first MOS transistor configured to apply a DC control voltage to said gate terminal of the first MOS transistor such that the first MOS transistor operates in a weak inversion or a sub-threshold region, wherein said control voltage causes a desired resistance value R between said first terminal and said second terminal of the first MOS transistor.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2019
From: OPTIS CIRCUIT TECHNOLOGY, LLC,
To: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
Reel/Frame 048529/0510 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2019
From: ST-ERICSSON SA, EN LIQUIDATION
To: OPTIS CIRCUIT TECHNOLOGY, LLC,
Reel/Frame 048504/0519 →
STATUS CHANGE-ENTITY IN LIQUIDATION Recorded Feb 2, 2016
From: ST-ERICSSON SA
To: ST-ERICSSON SA, EN LIQUIDATION
Reel/Frame 037739/0493 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 18, 2014
From: NICOLLINI, GERMANO; BARBIERI, ANDREA
To: ST-ERICSSON SA
Reel/Frame 033555/0317 →
Priority Claims (1)
EP 12159979 · Mar 16, 2012 · regional
Continuity (2)
Provisional Application 61612796 · Mar 19, 2012
Related Publication 20150035591A1 · Feb 5, 2015