IP Library Granted Patent US 9,653,509
Granted Patent B2
US 9,653,509 · App. 14/379,895 · Granted May 16, 2017

Image sensor and electronic device

Inventors: Toshiyuki Nishihara (Kanagawa, JP); Hirofumi Sumi (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H01L27/14643H01L27/14609H01L27/14616H04N5/378H04N5/3745
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Quick Facts
Patent No.
US 9,653,509
App. No.
14/379,895
Granted
May 16, 2017
Kind
B2
Abstract

There is provided an image sensor including pixels each configured to include a transfer transistor configured as an embedded channel type MOS transistor and to output a pixel signal based on a charge transferred to a floating diffusion from a photodiode by the transfer transistor in an on state, and a determination unit configured to convert the output pixel signal to a digital value, then compare the converted digital value to a threshold value, and thereby make a binary determination on presence or absence of incidence of a photon on the pixel that has generated the pixel signal.

Claims (35)

1. An image sensor comprising:

a plurality of pixels, wherein a respective one of the plurality of pixels includes a transfer transistor configured as an embedded channel type MOS transistor and is configured to output a pixel signal based on a charge transferred to a floating diffusion from a photodiode by the transfer transistor in an on state; and

a determination unit configured to convert the respective output pixel signal to a digital value, then compare the converted digital value to a threshold value, and thereby make a binary determination on presence or absence of incidence of a photon on the corresponding pixel that has generated the pixel signal.

2. The image sensor according to claim 1 ,

wherein the photodiode includes a charge accumulation region constituted by a first conductive impurity diffusion layer,

wherein the floating diffusion is constituted by the first conductive impurity diffusion layer, and

wherein the transfer transistor includes a channel region serving as a channel between the photodiode and the floating diffusion, and the channel region is constituted by the first conductive impurity diffusion layer having a concentration equal to or higher than 1×10 15 atoms/cm 3 .

3. The image sensor according to claim 2 , wherein the channel region has a peak of impurities formed in a depth within 0.2 μm from a substrate surface on a side on which a gate electrode of the transfer transistor is formed.

4. The image sensor according to claim 2 , wherein, when the transfer transistor is in an off state, the channel region functions as an overflow drain for discharging surplus charges from the charge accumulation region to the impurity diffusion layer.

5. The image sensor according to claim 2 , wherein, as the transfer transistor modulates a potential on a substrate surface that a gate electrode of the transfer transistor faces in a direction in which the potential becomes shallow using a difference of work functions of the gate electrode and the substrate that the gate electrode faces, the channel is formed in a position away from the substrate surface that the gate electrode faces toward the inside of the substrate.

6. The image sensor according to claim 2 , wherein the transfer transistor has a peak of impurities formed in a depth within 0.2 μm from a substrate surface on the side on which a gate electrode of the transfer transistor is formed, and a second conductive impurity diffusion layer is formed between the peak of the impurities and the gate electrode.

7. An image sensor comprising:

a plurality of pixels, wherein a respective one of the plurality of pixels includes a transfer transistor configured as an embedded channel type MOS transistor and is configured to output a pixel signal based on a charge transferred to a floating diffusion from a photodiode by the transfer transistor in an on state; and

a determination unit configured to convert the respective output pixel signal to a digital value, then compare the converted digital value to a plurality of threshold values, and thereby make a determination on the number of photons incident on the corresponding pixel that has generated the pixel signal.

8. An electronic device comprising:

a plurality of pixels, wherein a respective one of the plurality of pixels includes a transfer transistor configured as an embedded channel type MOS transistor and is configured to output a pixel signal based on a charge transferred to a floating diffusion from a photodiode by the transfer transistor in an on state; and

a determination unit configured to convert the respective output pixel signal to a digital value, then compare the converted digital value to a threshold value, and thereby make a binary determination on presence or absence of incidence of a photon on the corresponding pixel that has generated the pixel signal.

9. The image sensor according to claim 1 , wherein the threshold value is an intermediate value between a first digital value corresponding to a state of presence of a photon incidence on the corresponding pixel and a second digital value corresponding to a state of absence of a photon on the corresponding pixel.

10. The image sensor according to claim 1 , wherein the threshold value is a predetermined value.

11. The image sensor according to claim 7 ,

wherein the photodiode includes a charge accumulation region constituted by a first conductive impurity diffusion layer,

wherein the floating diffusion is constituted by the first conductive impurity diffusion layer, and

wherein the transfer transistor includes a channel region serving as a channel between the photodiode and the floating diffusion, and the channel region is constituted by the first conductive impurity diffusion layer having a concentration equal to or higher than 1×10 15 atoms/cm 3 .

12. The image sensor according to claim 11 , wherein the channel region has a peak of impurities formed in a depth within 0.2 μm from a substrate surface on a side on which a gate electrode of the transfer transistor is formed.

13. The image sensor according to claim 11 , wherein, when the transfer transistor is in an off state, the channel region functions as an overflow drain for discharging surplus charges from the charge accumulation region to the impurity diffusion layer.

14. The image sensor according to claim 11 , wherein, as the transfer transistor modulates a potential on a substrate surface that a gate electrode of the transfer transistor faces in a direction in which the potential becomes shallow using a difference of work functions of the gate electrode and the substrate that the gate electrode faces, the channel is formed in a position away from the substrate surface that the gate electrode faces toward the inside of the substrate.

15. The image sensor according to claim 11 wherein the transfer transistor has a peak of impurities formed in a depth within 0.2 μm from a substrate surface on the side on which a gate electrode of the transfer transistor is formed, and a second conductive impurity diffusion layer is formed between the peak of the impurities and the gate electrode.

16. The image sensor according to claim 7 , wherein a respective one of the plurality of threshold values is an intermediate value between a first digital value corresponding to a state of incidence of n photons on the corresponding pixel and a second digital value corresponding to a state of incidence of n+1 photons on the corresponding pixel, where n is a whole number.

17. The image sensor according to claim 7 , wherein the plurality of threshold values is a plurality of predetermined values.

18. The electronic device according to claim 8 ,

wherein the photodiode includes a charge accumulation region constituted by a first conductive impurity diffusion layer,

wherein the floating diffusion is constituted by the first conductive impurity diffusion layer, and

wherein the transfer transistor includes a channel region serving as a channel between the photodiode and the floating diffusion, and the channel region is constituted by the first conductive impurity diffusion layer having a concentration equal to or higher than 1×10 15 atoms/cm 3 .

19. The electronic device according to claim 18 , wherein the channel region has a peak of impurities formed in a depth within 0.2 μm from a substrate surface on a side on which a gate electrode of the transfer transistor is formed.

20. The electronic device according to claim 18 , wherein, when the transfer transistor is in an off state, the channel region functions as an overflow drain for discharging surplus charges from the charge accumulation region to the impurity diffusion layer.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE ZIP CODE FROM 246-0014 TO 243-0014 PREVIOUSLY RECORDED AT REEL: 039645 FRAME: 0019. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 13, 2016
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 040894/0926 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2016
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 039645/0019 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 20, 2014
From: NISHIHARA, TOSHIYUKI; SUMI, HIROFUMI
To: SONY CORPORATION
Reel/Frame 033573/0180 →
Priority Claims (1)
JP 2012-039561 · Feb 27, 2012 · national
Continuity (1)
Related Publication 20150021461A1 · Jan 22, 2015