High-voltage voltage-switched class-S amplifier
A voltage-switched class-S amplifier circuit includes an output stage configured to receive at least one control signal and operative to generate an output signal as a function of the at least one control signal. The amplifier circuit further includes a driver circuit coupled with the output stage. The driver circuit is configured to receive an input bit stream signal and is operative to generate the control signal as a function of the input bit stream signal in such a manner that a common mode component is eliminated from the control signal.
1. A voltage-switched class-S amplifier circuit, comprising:
an output stage configured to receive at least one control signal and operative to generate an output signal as a function of the at least one control signal; and
a driver circuit coupled with the output stage, the driver circuit being configured to receive an input bit stream signal and being operative to generate the at least one control signal as a function of the input bit stream signal, wherein the driver circuit comprises an isolation circuit connected in a signal path between the output stage and the input bit stream signal, the isolation circuit being operative to electrically isolate the input bit stream signal from the at least one control signal.
2. The amplifier circuit of claim 1 , wherein the isolation circuit comprises a voltage level shifter circuit including a first stage referenced to a first voltage supply and a second stage referenced to a second voltage supply, the voltage level shifter circuit including a signal path between the first and second stages that is electrically isolated from one another.
3. The amplifier circuit of claim 2 , further comprising a signal generator circuit operative to receive an input signal supplied to the amplifier circuit and to generate the second voltage supply as a function thereof.
4. The amplifier circuit of claim 3 , wherein the signal generator circuit comprises a full-wave rectifier circuit, the full-wave rectifier circuit comprising:
a bridge rectifier; and
a transformer including a primary winding adapted to receive the input signal, and a secondary winding connected with first and second terminals of the bridge rectifier, the second voltage supply being generated across third and fourth terminals of the bridge rectifier.
5. The amplifier circuit of claim 4 , wherein the transformer exhibits an inter-winding capacitance which is less than about two picofarads.
6. The amplifier circuit of claim 3 , wherein the input signal is a clock signal.
7. The amplifier circuit of claim 1 , wherein the isolation circuit comprises an optical isolator.
8. The amplifier circuit of claim 1 , wherein the output stage comprises a differential output stage configured to receive the first control signal and at least a second control signal, and wherein the driver circuit comprises a differential driver circuit adapted to receive a differential bit stream and to generate the first and second control signals as a function of the differential bit stream, the differential driver circuit comprising:
an isolation circuit connected in a first signal path between the differential output stage and a first input bit stream signal of the differential bit stream, the isolation circuit being operative to electrically isolate the first input bit stream signal from the first control signal; and
a delay circuit connected in a second signal path between the differential output stage and a second input bit stream signal of the differential bit stream, the delay circuit being operative to generate the second control signal as a delayed version of the second input bit stream signal.
9. The amplifier circuit of claim 8 , wherein the driver circuit further comprises a differential bit stream generator operative to generate the first and second input bit stream signals.
10. The amplifier circuit of claim 8 , wherein the delay circuit has a first delay associated therewith which is configured to match a second delay associated with the isolation circuit.
11. The amplifier circuit of claim 1 , wherein the driver circuit comprises a bit stream generator operative to generate the input bit stream signal.
12. The amplifier circuit of claim 11 , wherein the bit stream generator comprises a differential bit stream generator operative to generate a differential input bit stream signal, the differential input bit stream signal comprising first and second input bit stream signals that are logical complements of one another.
13. The amplifier circuit of claim 1 , wherein the output stage is configured to receive at least first and second control signals, the output stage comprising at least first and second n-channel field-effect transistors, a first source/drain of the first n-channel field-effect transistor being connected with a first voltage supply, a second source/drain of the first n-channel field-effect transistor being connected with a first source/drain of the second n-channel field-effect transistor, a second source/drain of the second n-channel field-effect transistor being connected with a second voltage supply, a gate of the first n-channel field-effect transistor being configured to receive the first control signal, and a gate of the second n-channel field-effect transistor being configured to receive the second control signal.
14. The amplifier circuit of claim 1 , wherein at least a portion of the amplifier circuit is fabricated in at least one integrated circuit.
15. The amplifier circuit of claim 1 , further comprising:
a bit stream generator operative to generate the input bit stream signal, wherein the bit stream generator is internal to the driver circuit.
16. A driver circuit for use with a high-voltage, voltage-switched class-S amplifier circuit, the driver circuit comprising:
a driver stage configured for connection with an output stage of the amplifier circuit, the driver stage being configured to receive at least one control signal and to generate at least one drive signal as a function of the at least one control signal for driving the output stage of the amplifier circuit; and
an isolation circuit connected with the driver stage, the isolation circuit being configured to receive an input bit stream signal and being operative to generate the at least one control signal as a function of the input bit stream signal.
17. The driver circuit of claim 16 , wherein the driver stage comprises a differential driver stage adapted to receive a differential bit stream and to generate the first and second control signals as a function of the differential bit stream, the differential driver stage comprising:
the isolation circuit connected in a first signal path between a differential output stage connected with the driver circuit and a first input bit stream signal of the differential bit stream, the isolation circuit being operative to electrically isolate the first input bit stream signal from the first control signal; and
a delay circuit connected in a second signal path between the differential output stage and a second input bit stream signal of the differential bit stream, the delay circuit being operative to generate the second control signal as a delayed version of the second input bit stream signal.
18. The driver circuit of claim 17 , wherein the delay circuit has a first delay associated therewith which is configured to match a second delay associated with the isolation circuit.
19. The driver circuit of claim 16 , wherein the isolation circuit comprises a voltage level shifter circuit including a first stage referenced to a first voltage supply and a second stage referenced to a second voltage supply, the voltage level shifter circuit including a signal path between the first and second stages that is electrically isolated from one another.
20. An electronic system, comprising at least one voltage-switched class-S amplifier circuit, the at least one voltage-switched class-S amplifier circuit comprising:
an output stage configured to receive at least one control signal and operative to generate an output signal as a function of the at least one control signal; and
a driver circuit coupled with the output stage, the driver circuit being configured to receive an input bit stream signal and being operative to generate the at least one control signal as a function of the input bit stream signal, wherein the driver circuit comprises an isolation circuit connected in a signal path between the output stage and the input bit stream signal, the isolation circuit being operative to electrically isolate the input bit stream signal from the at least one control signal.