IP Library Granted Patent US 9,437,508
Granted Patent B2
US 9,437,508 · App. 14/381,133 · Granted Sep 6, 2016

Method for manufacturing semiconductor device and semiconductor device

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Quick Facts
Patent No.
US 9,437,508
App. No.
14/381,133
Granted
Sep 6, 2016
Kind
B2
Abstract

In a method for manufacturing a semiconductor device according to the present invention, as shown in FIG. 2 (A), a case ( 2 ) including a first terminal ( 1 ) is placed on a working table ( 3 ) with an opening ( 30 ) formed at the bottom of the case ( 2 ). Subsequently, as shown in FIG. 2 (B), a plurality of packages ( 6,6,6 ) including second terminals ( 4 ) are placed on the working table ( 3 ) through the opening ( 30 ) of the case ( 2 ), forming a clearance ( 31 ) between the first terminal ( 1 ) and the second terminal ( 4 ). As shown in FIG. 2 (C), a bonding material ( 7 ) is disposed in the clearance ( 31 ) so as to electrically connect the first terminal ( 1 ) and the second terminal ( 4 ). Thus, the exposed surfaces of the packages ( 6,6,6 ) in the opening ( 30 ) of the case ( 2 ) are aligned at the same height, thereby reducing variations in thermal resistance among the packages ( 6,6,6 ).

Claims (9)

1. A method for manufacturing a semiconductor device including a plurality of packages disposed in a resin-molded case, the package containing a power semiconductor element,

the method comprising:

placing a bottom of the case on a working table with an opening formed at the bottom, the case including a first terminal with one end internally drawn along the bottom of the case for connecting to the power semiconductor element;

placing the package on the working table through the opening of the case, the package including a second terminal connected to the power semiconductor element, disposing a first faying surface that is a top surface of the first terminal of the case and a second faying surface that is an undersurface of the second terminal of the package in such a manner that the first faying surface and the second faying surface are opposed to each other, and forming a clearance between the first faying surface and the second faying surface; and

electrically connecting the first terminal and the second terminal with a bonding material disposed in the clearance.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein the first terminal and the second terminal are joined to each other by heating and melting Sn solder used as a bonding material.

3. The method for manufacturing a semiconductor device according to claim 1 , wherein the second terminal is plated with Sn used as a principal component.

4. The method for manufacturing a semiconductor device according to claim 1 , wherein the package includes a third terminal drawn in a direction that separates from the working table along the depth direction of the case, and a control board including a circuit configured to output a driving signal to the power semiconductor element is electrically connected to the third terminal before or after the package is placed on the working table.

5. The method for manufacturing a semiconductor device according to claim 1 , wherein one of the first terminal and the second terminal is composed of one of Cu and a Cu alloy.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 23, 2015
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 034794/0940 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2014
From: TANAKA, ZYUNYA; MINAMIO, MASANORI
To: PANASONIC CORPORATION
Reel/Frame 034275/0853 →