Data processing method, precoding method, and communication device

1. A data processing scheme comprising:

an encoding step of outputting a first bit sequence that is an N-bit codeword from a K-bit information bit sequence;

a mapping step of generating a first complex signal s 1 and a second complex signal s 2 with use of a bit sequence having X+Y bits included in an input second bit sequence, where X indicates the number of bits used to generate the first complex signal s 1 , and Y indicates the number of bits used to generate the second complex signal s 2 ; and

a bit length adjustment step of, after the encoding step and before the mapping step, performing bit length adjustment on the first bit sequence such that the second bit sequence has a bit length that is a multiple of X+Y, and outputting the first bit sequence after the bit length adjustment as the second bit sequence.

2. The data processing scheme of claim 1 , wherein

the encoding step performs accumulate processing on a bit sequence of a parity portion of N−K bits that is generated by performing a systematic LDPC coding, and

the bit length adjustment step generates an adjustment bit sequence by performing at least one repetition of a bit value of a predetermined bit of a bit sequence resulting from the accumulate processing, and performs the bit length adjustment with use of the adjustment bit sequence.

3. The data processing scheme of claim 1 , wherein

the encoding step includes interleave processing on the first bit sequence, and

the bit length adjustment step is performed after the interleave processing.

4. The data processing scheme of claim 1 , further comprising

before the encoding step, a front end processing step of giving the K-bit information bit sequence to be processed by the encoding step, wherein

the front end processing step generates the K-bit information bit sequence by reserving in advance, in the K-bit information bit sequence, a field into which the adjustment bit sequence is to be temporarily inserted, and inserting the adjustment bit sequence into the field, and

the bit length adjustment step removes bits of the adjustment bit sequence that is temporarily inserted.

5. The data processing scheme of claim 2 , wherein

the predetermined bit is a last bit of the bit sequence resulting from the accumulate processing.

6. The data processing scheme of claim 3 , wherein

the interleave processing is performed by writing a bit sequence targeted for interleaving to a memory having a size of Nr×Nc in a predetermined write order, and reading the written bit sequence from the memory in a read order that differs from the write order, where Nr and Nc are divisors of the number of bits of the first bit sequence, and

the bit length adjustment step outputs, as the second bit sequence, a result of the bit interleave processing to which a bit sequence having a predetermined number of bits are added.

7. The data processing scheme of claim 4 , wherein

the bits of the adjustment bit sequence that is temporarily inserted each have a bit value of zero.

8. A bit sequence decoding scheme comprising:

a demapping step of outputting a first data sequence corresponding to a bit sequence having a bit length that is a multiple of X+Y, the first data sequence being based on a data sequence corresponding to a bit sequence having X+Y bits generated from a first complex signal s 1 and a second complex signal s 2 , where X indicates the number of bits used to generate the first complex signal s 1 , and Y indicates the number of bits used to generate the second complex signal s 2 ;

a deinterleaving step of deinterleaving a second data sequence corresponding to a bit sequence having N bits with use of a memory, and outputting the deinterleaved second data sequence, the memory having memory regions equal in number to a divisor of the N bits and whose addresses are consecutive, and storing each of pieces of data corresponding one-to-one to bits of the bit sequence having the N bits in a different one of the memory regions;

an error-correction decoding step of performing error correction decoding on the deinterleaved second data sequence to generate a K-bit information bit sequence, and outputting the K-bit information bit sequence; and

before the deinterleaving step, a bit length adjustment step of removing a data sequence corresponding to an adjustment bit sequence from the first data sequence to generate the second data sequence, and outputting the second data sequence.

9. A bit sequence decoding scheme comprising:

a demapping step of outputting a first data sequence corresponding to a bit sequence having a bit length that is a multiple of X+Y, the first data sequence being based on a data sequence corresponding to a bit sequence having X+Y bits generated from a first complex signal s 1 and a second complex signal s 2 , where X indicates the number of bits used to generate the first complex signal s 1 , and Y indicates the number of bits used to generate the second complex signal s 2 ;

a bit length adjustment step of extracting a predetermined data sequence from the first data sequence, performing statistical processing on the extracted predetermined data sequence to generate a second data sequence corresponding to a bit sequence having N bits, and outputting the second data sequence; and

an error-correction decoding step of performing error correction decoding on the second data sequence after the statistical processing to generate a K-bit information bit sequence, and outputting the K-bit information bit sequence.