Data speculation for array processors

1. A method of utilizing a plurality of Arithmetic Logic Units (ALUs) of an array processor comprising:

determining that a first quantity of the ALUs are scheduled to execute a function during a given processing cycle, with each ALU being scheduled to use a respective one of a plurality of selected input vectors as an input;

determining that a second quantity of the ALUs are not scheduled for use during the given processing cycle;

determining a plurality of predicted future input vectors that differ from the plurality of selected input vectors;

scheduling the second quantity of ALUs to execute the function during the given processing cycle using respective ones of the plurality of predicted future input vectors as inputs; and

after completion of the processing cycle, caching function outputs received from the first and second quantity of ALUs.

2. The method of claim 1 , wherein said determining the plurality of predicted future input vectors comprises:

selecting one or more previous input vectors that have been used as inputs for the function in one or more previous processing cycles; and

applying one or more genetic algorithms to the one or more previous input vectors to determine at least a portion of the plurality of predicted future input vectors.

3. The method of claim 2 , further comprising:

incrementing a fitness score for a given input vector each time that the input vector is selected as an input for the function;

wherein said selecting one or more previous input vectors that have been used as inputs for the function in one or more previous processing cycles is performed based the fitness scores of the previous input values.

4. The method of claim 2 :

wherein applying one or more genetic algorithms to the one or more previous input vectors comprises performing a genetic crossover on two previous input vectors to determine two different, new input vectors.

5. The method of claim 4 , further comprising applying a mutation operator to one or more elements in one or both of the new input vectors.

6. The method of claim 5 , wherein the mutation operator comprises one of: replacing a value of an element of an input vector with a random value, negating a value of an element of an input vector; increasing a value of an element of an input vector by a predefined amount, and decreasing a value of an element of an input vector by a predefined amount.

7. The method of claim 1 :

wherein the selected input vectors are part of a larger set of input vectors; and

wherein determining the plurality of predicted future input vectors that differ from the plurality of selected input vectors comprises randomly selecting input vectors from the set of input vectors that have not yet been used as inputs to the function as the predicted input vectors.

8. A computing device comprising:

an array processor comprising a plurality of Arithmetic Logic Units (ALUs); and

a processing circuit configured to:

determine that a first quantity of the ALUs are scheduled to execute a function during a given processing cycle, with each ALU being scheduled to use a respective one of a plurality of selected input vectors as an input;

determine that a second quantity of the ALUs are not scheduled for use during the given processing cycle;

determine a plurality of predicted future input vectors that differ from the plurality of selected input vectors;

schedule the second quantity of ALUs to execute the function during the given processing cycle using respective ones of the plurality of predicted future input vectors as inputs; and

after completion of the processing cycle, cache function outputs received from the first and second quantity of ALUs.

9. The computing device of claim 8 , wherein to determine the plurality of predicted future input vectors, the processing circuit is configured to:

select one or more previous input vectors that have been used as inputs for the function in one or more previous processing cycles; and

apply one or more genetic algorithms to the one or more previous input vectors to determine at least a portion of the plurality of predicted future input vectors.

10. The computing device of claim 9 , wherein the processing circuit is further configured to:

increment a fitness score for a given input vector each time that the input vector is selected as an input for the function;

wherein the selection of the one or more previous input vectors that have been used as inputs for the function in one or more previous processing cycles is performed based on the fitness score of the previous input values.

11. The computing device of claim 9 :

wherein to apply one or more genetic algorithms to the one or more previous input vectors, the controller circuit is configured to perform a genetic crossover on two previous input vectors to determine two different, new input vectors.

12. The computing device of claim 11 , wherein the processing circuit is further configured to apply a mutation operator to one or more elements in one or both of the new input vectors.

13. The computing device of claim 12 , wherein the mutation operator comprises one of: replacing a value of an element of an input vector with a random value, negating a value of an element of an input vector; increasing a value of an element of an input vector by a predefined amount, and decreasing a value of an element of an input vector by a predefined amount.

14. The computing device of claim 8 :

wherein the selected input vectors are part of a larger set of input vectors; and

wherein to determine the plurality of predicted future input vectors that differ from the plurality of selected input vectors, the processing circuit is configured to randomly select input vectors from the set of input vectors that have not yet been used as inputs to the function as the predicted input vectors.

15. The computing device of claim 8 , wherein the array processor includes a Graphics Processing Unit (GPU).