Selective partitioning of via structures in printed circuit boards
The embodiments herein relate to a method for selective partitioning of a via in a printed circuit board as to produce an electrically isolating portion between two electrically conducting portions in said via. The method involves the step of prior to drilling the hole for the via, laminating plating resist layers to the printed circuit board at a distance from each other corresponding to a desired length of the electrically isolated portion of the via. After drilling, copper is added to selected portions of the interior of the via in two different processing steps followed by a step of removing undesired copper as to produce the electrically isolating portion.
1. A method of partitioning a via in a multilayer printed circuit board as to produce an electrically isolating portion between two electrically conducting portions in said via, the method comprising of:
placing at least one island of a first plating resist layer on a first layered structure comprising a first conductive layer and a first dielectric layer, and placing at least one island of a second plating resist layer on a second layered structure comprising a second conductive layer and a second dielectric layer;
laminating the first and second layered structures with a third intermediate layered structure comprising at least one third dielectric layer adapted so that the islands of the first and second plating resist layers become embedded in the at least one third dielectric layer;
drilling a first hole in the printed circuit board so that the first hole passes through the islands of the first and the second plating resist layer;
placing said circuit board in a copper seed catalyzing bath so that a first copper layer is placed on an interior of the first hole except for portions with the plating resist layer;
placing the printed circuit board in an electrolytic copper plating bath where the first copper layer placed on the at least one third dielectric layer portion of the first hole is electrically isolated from the first and second conductive layers so that additional copper is placed on the interior of the first hole except for portions of the first and second plating resist layers and except for portion of the at least one third dielectric layer;
removing the first copper layer placed on the at least one third dielectric layer portion of the first hole after the electrolytic copper plating bath.
2. The method of claim 1 , wherein the third processing step of removing copper from the at least one third dielectric layer portion of the first hole is done by microetching.
3. The method of claim 1 , wherein the at least one third dielectric layer is made of an impregnated fiber weave adapted to embed the islands of the first and second plating resist layers.
4. The method of claim 1 , wherein the first hole is partly penetrating the printed circuit board.
5. The method of claim 1 , wherein the first hole is a through hole through the printed circuit board.
6. The method of claim 5 , wherein the step of drilling the first hole comprises the additional step of drilling with a larger drill from the opposite side of the printed circuit board as to produce two portions of the via with different diameters and wherein the two via portions meet each other in a position between the first and second plating resist layers.