Thin film transistor, manufacturing method thereof and array substrate

1. A thin film transistor, comprising a gate electrode, a gate insulation layer, an active layer, a source electrode and a drain electrode provided on a base substrate, wherein along a direction perpendicular to the base substrate, the source electrode and the drain electrode are respectively provided at opposite both sides of the active layer, and the source electrode and the drain electrode contacts the active layer;

wherein the gate electrode end the source/drain electrode are provided in the same layer, the gate electrode is not connected with the source/drain electrode and the gate insulation layer is provided between the gate electrode and the active layer;

wherein the drain electrode is provided between the base substrate and the active layer, and the source electrode is provided at a side of the active layer away from the base substrate.

2. The thin film transistor according to claim 1 , wherein the gate insulation layer is provided between the source electrode and the active layer, and the source electrode contacts the active layer through a first through hole provided in the gate insulation layer.

3. The thin film transistor according to claim 1 , wherein the active layer comprises a three-layer structure comprising an ohmic contact layer/an amorphous silicon semiconductor layer/an ohmic contact layer.

4. The thin film transistor according to claim 1 , wherein the active layer is a metal oxide semiconductor active layer.

5. An array substrate, comprising a thin film transistor according to claim 1 .

6. The array substrate according to claim 5 , further comprising a protection layer and a pixel electrode,

the drain electrode of the thin film transistor is provided between the base substrate and the active layer, the gate insulation layer is provided between the source electrode and the active layer, the source electrode contacts the active layer through a first through hole provided in the gate insulation layer, the gate electrode and the source electrode are provided in the same layer and are electrically insulated from each other, the gate insulation layer is provided between the gate electrode and the active layer, the protection layer is provided on the gate electrode and the source electrode, and the pixel electrode is connected with the drain electrode through a second through hole provided in the protection layer and a third through hole in the gate insulation layer.

7. The array substrate according to claim 5 , further comprising a protection layer and a pixel electrode,

the drain electrode of the thin film transistor is provided between the base substrate and the active layer, the gate insulation layer is provided between the source electrode and the active layer, the source electrode contacts the active layer through a first through hole provided in the gate insulation layer, the gate electrode and the source electrode are provided in the same layer and are electrically insulated from each other, the gate insulation layer is provided between the gate electrode and the active layer, the protection layer is provided on the gate electrode and the source electrode, and the pixel electrode is connected with the source electrode through a second through hole provided in the protection layer.

8. The array substrate according to claim 6 , further comprising:

a passivation layer, covering the pixel electrode; and

a common electrode, provided on the passivation layer.

9. The array substrate according to claim 6 , wherein the active layer comprises a three-layer structure comprising an ohmic contact layer/an amorphous silicon semiconductor layer/an ohmic contact layer.

10. The array substrate according to claim 6 , wherein the active layer is a metal oxide semiconductor active layer.

11. A method for manufacturing a thin film transistor, comprising:

forming a gate electrode, a gate insulation layer, an active layer, a source electrode and a drain electrode on a base substrate,

wherein the source electrode and the drain electrode are respectively provided at opposite both sides of the active layer along a direction perpendicular to the base substrate, and the source electrode and the drain electrode contacts the active layer;

wherein the gate electrode and the source electrode/drain electrode are formed in one same patterning process, and the gate electrode is not connected with the source electrode/drain electrode, and the gate insulation layer is provided between the gate electrode and the active layer,

wherein the forming the source electrode and the drain electrode at opposite both sides of the active layer comprises: forming the drain electrode between the base substrate and the active layer, and forming the source electrode at a side of the active layer away from the base substrate.

12. The method according to claim 11 , wherein the forming the source electrode at a side of the active layer away from the base substrate comprises: forming the gate insulation layer between the source electrode and the active layer, wherein the source electrode contacts the active layer through a through hole formed in the gate insulation layer.