IP Library Granted Patent US 9,419,605
Granted Patent B2
US 9,419,605 · App. 14/390,536 · Granted Aug 16, 2016

Composite semiconductor switching device

Inventor: Junichiro Ishikawa (Tokyo, JP)
Assignee: Mitsubishi Electric Corporation
H03K17/56H02M1/08H02M1/088H03K17/164H02M2001/0054H03K2217/0036H03K2217/0054Y02B70/1491
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Quick Facts
Patent No.
US 9,419,605
App. No.
14/390,536
Granted
Aug 16, 2016
Kind
B2
Abstract

A composite semiconductor switching device includes: a first semiconductor element that incurs switching losses when performing switching operation of turning on and off; a second semiconductor element that is parallelly connected to the first semiconductor element and incurs switching losses larger than the first semiconductor element when performing switching operations of turning on and off; and a controller that operates in order of giving a first on-command signal to the first semiconductor element, giving a second on-command signal to the second semiconductor element, deactivating the first on-command signal, giving a third on-command signal to the first semiconductor element, and deactivating the second on-command signal.

Claims (7)

1. A composite semiconductor switching device comprising:

a first semiconductor element that incurs switching losses when performing switching operation of turning on and off;

a second semiconductor element that is parallelly connected to the first semiconductor element and incurs switching losses larger than the first semiconductor element when performing switching operations of turning on and off; and

a control means that operates in order of giving a first on-command signal to the first semiconductor element, giving a second on-command signal to the second semiconductor element, deactivating the first on-command signal, giving a third on-command signal to the first semiconductor element, and deactivating the second on-command signal.

2. The composite semiconductor switching device according to claim 1 , wherein the control means generates the first and second on-command signals so that after the second on-command signal builds up, a period overlapping between the second on-command signal and the first on-command signal is a turn-on time of the second semiconductor element or longer, but is twice the turn-on time or shorter.

3. The composite semiconductor switching device according to claim 1 , wherein the control means generates the second and third on-command signals so that after the third on-command signal builds up, a period overlapping between the third on-command signal and the second on-command signal is a turn-off time of the second semiconductor element or longer, but is twice the turn-off time or shorter.

4. The composite semiconductor switching device according to claim 2 , wherein the control means generates the second and third on-command signals so that after the third on-command signal builds up, a period overlapping between the third on-command signal and the second on-command signal is a turn-off time of the second semiconductor element or longer, but is twice the turn-off time or shorter.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2014
From: ISHIKAWA, JUNICHIRO
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 034147/0932 →
Continuity (1)
Related Publication 20150116024A1 · Apr 30, 2015