Shift register having multiple output units connected in cascade as display device scan line driving circuit

1. A shift register, comprising:

unit circuits connected in a cascade, the unit circuits each including a first output unit, a second output unit, and a logic circuit,

the first output unit including a driving output terminal for outputting a driving signal; a first transistor for applying a first voltage to the driving output terminal; and a second transistor for applying a second voltage lower than the first voltage to the driving output terminal,

the second output unit including an output-to-next terminal for outputting a signal to a next unit circuit in the cascade; a third transistor for applying a third voltage to the output-to-next terminal; and a fourth transistor for applying a fourth voltage lower than the third voltage to the output-to-next terminal, and

the logic circuit including a first signal generator unit configured to generate a first signal for switching the first transistor and the third transistor between a conducting state and a non-conducting state according to the signal provided from a preceding unit circuit in the cascade; and a second signal generator unit configured to generate a second signal for switching the second transistor and the fourth transistor between the conducting state and the non-conducting state according to the signal provided from the preceding unit circuit in the cascade,

wherein the first transistor and the second transistor each have a current supply capability larger than a current supply capability of the third transistor and a current supply capability of the fourth transistor,

the second voltage is set at a fixed potential higher than the fourth voltage,

the first transistor includes a control terminal to which the first signal is input, a first output terminal, and a second output terminal connected to the driving output terminal,

the first output terminal is connected to a signal source of a clock signal having a high level at the first voltage and a low level at a voltage lower than the first voltage,

the logic circuit electrically disconnects the control terminal and the first signal generator at least for a predetermined period starting immediately before the clock signal changes from the high level to the low level,

the predetermined period including a low level period after the clock signal changes from the high level to the low level, the low level period being a period during which the clock signal continues to have the low level, and

the first transistor remains in the conducting state and the second transistor is turned up to the conducting state by the second signal generator in the low level period.

2. The shift register according to claim 1 ,

wherein the logic circuit is connected to a high voltage source and a low voltage source for generating the first signal and the second signal, and

the fourth voltage is set at a potential same as output voltage of the low voltage source.

3. The shift register according to claim 2 , further comprising:

a capacitor connected between the control terminal and the second output terminal of the first transistor,

wherein potential of the control terminal changes from the fourth voltage to a voltage lower than the fourth voltage when the clock signal changes to the low level.

4. The shift register according to claim 2 ,

wherein the low level is a potential same as the fourth voltage.

5. A display device comprising:

ft register according to claim 1 ;

scan lines for transmitting driving signals output from the shift register;

signal lines for transmitting a video signal, the signal lines, the signal lines crossing the scan lines; and

a display including pixel circuits each of which is disposed at a different one of crosspoints of the scan lines and the signal lines and, under control of the driving signals, emits light corresponding to the video signal.