Surface mountable semiconductor device

1. A surface mountable semiconductor device comprising:

at least one semiconductor element mounted on or integrated in a device substrate,

the device substrate having a top surface and a bottom surface, the top surface being proximate to the at least one semiconductor element and the bottom surface being distal from the at least one semiconductor element,

one or more electrical connection pads distinct from the device substrate, the one or more electrical connection pads being arranged on the bottom surface of the device substrate, the one or more electrical connection pads having a first height, and

at least one thermal pad distinct from the device substrate, the at least one thermal pad being arranged on the bottom surface of the device substrate, the at least one thermal pad having a second height that is larger than the first height of the one or more electrical connection pads, wherein the surface mountable semiconductor device is surface mountable through an electrical connection through a bottom of the one or more electrical connection pads,

wherein the at least one thermal pad is separated from the one or more electrical connection pads by a trench or gap and the trench or gap is filled with an electrically insulating material.

2. The device according to claim 1 , wherein the at least one thermal pad is arranged at a central portion of the bottom surface.

3. The device according to claim 1 , wherein a difference between the first height and the second height is between 20 and 300 μm.

4. The device according to claim 1 , wherein a difference between the first height and the second height is between 40 and 100 μm.

5. The device according to claim 1 , wherein the at least one semiconductor element is a light emitting diode.

6. An arrangement of one or several surface mountable semiconductor devices according to claim 1 mounted on a carrier substrate, the carrier substrate at least comprising a metallic plate or metallic core layer covered by a dielectric layer on which an electrically conductive layer is arranged, wherein the electrically conductive layer and the dielectric layer are not present or removed underneath the at least one thermal pad of the device and underneath at least part of the trench or the gap, the at least one thermal pad being thermally connected by a thermal interconnect layer to the metallic plate or metallic core layer and the one or more electrical connection pads being electrically connected by an electrical interconnect layer to the electrically conductive layer.

7. The arrangement of claim 6 , wherein the carrier substrate is an insulated metal substrate or a metal core printed circuit board.

8. The arrangement of claim 6 , wherein the thermal interconnect layer to the metallic plate or metallic core layer and the electrical interconnect layer of the one or more electrical connection pads and the electrically conductive layer are uniform deposition layers.

9. The arrangement of claim 6 , wherein the electrical interconnect layer is a deposition of solder paste.

10. The device according to claim 1 , wherein the at least one thermal pad and the one or more electrical connection pads are confined to a region that is no wider than the device substrate.

11. An arrangement, comprising:

a carrier substrate, the carrier substrate at least comprising a metallic plate or metallic core layer covered by a dielectric layer on which an electrically conductive layer is arranged; and

a surface mountable semiconductor device mounted on the carrier substrate, the surface mountable semiconductor device comprising:

at least one semiconductor element mounted on or integrated in a device substrate,

the device substrate having a top surface and a bottom surface, the top surface being proximate to the at least one semiconductor element and the bottom surface being distal from the at least one semiconductor element,

one or more electrical connection pads distinct from the device substrate, the one or more electrical connection pads being arranged on the bottom surface of the device substrate, the one or more electrical connection pads having a first height; and

at least one thermal pad distinct from the device substrate, the at least one thermal pad being arranged on the bottom surface of the device substrate, the at least one thermal pad having a second height that is larger than the first height of the one or more electrical connection pads, wherein the surface mountable semiconductor device is surface mountable through an electrical connection through a bottom of the one or more electrical connection pads;

wherein:

the at least one thermal pad is separated from the one or more electrical connection pads by a trench or gap;

the electrically conductive layer and the dielectric layer are not present or removed underneath the at least one thermal pad of the device and underneath at least part of the trench or the gap;

the at least one thermal pad being thermally connected by a thermal interconnect layer to the metallic plate or metallic core layer and the one or more electrical connection pads being electrically connected by an electrical interconnect layer to the electrically conductive layer; and

a difference in height of the first height and the second height equals a sum of thicknesses of the electrically conductive layer and the dielectric layer.

12. An arrangement, comprising:

a carrier substrate, the carrier substrate at least comprising a metallic plate or metallic core layer covered by a dielectric layer on which an electrically conductive layer is arranged; and

a surface mountable semiconductor device mounted on the carrier substrate, the surface mountable semiconductor device comprising:

at least one semiconductor element mounted on or integrated in a device substrate,

the device substrate having a top surface and a bottom surface, the top surface being proximate to the at least one semiconductor element and the bottom surface being distal from the at least one semiconductor element,

one or more electrical connection pads distinct from the device substrate, the one or more electrical connection pads being arranged on the bottom surface of the device substrate, the one or more electrical connection pads having a first height; and

at least one thermal pads distinct from the device substrate, the at least one thermal pad being arranged on the bottom surface of the device substrate, the at least one thermal pad having a second height that is larger than the first height of the one or more electrical connection pads, wherein the surface mountable semiconductor device is surface mountable through an electrical connection through a bottom of the one or more electrical connection pads;

wherein:

the at least one thermal pad is separated from the one or more electrical connection pads by a trench or gap;

the electrically conductive layer and the dielectric layer are not present or removed underneath the at least one thermal pad of the device and underneath at least part of the trench or the gap;

the at least one thermal pad being thermally connected by a thermal interconnect layer to the metallic plate or metallic core layer and the one or more electrical connection pads being electrically connected by an electrical interconnect layer to the electrically conductive layer; and

the thermal interconnect layer to the metallic plate or metallic core layer has a surface for the at least one thermal pad at the level of the surface of the dielectric layer facing the surface mountable semiconductor device.

13. An arrangement, comprising:

a carrier substrate, the carrier substrate at least comprising a metallic plate or metallic core layer covered by a dielectric layer on which an electrically conductive layer is arranged; and

a surface mountable semiconductor device mounted on the carrier substrate, the surface mountable semiconductor device comprising:

at least one semiconductor element mounted on or integrated in a device substrate,

the device substrate having a top surface and a bottom surface, the top surface being proximate to the at least one semiconductor element and the bottom surface being distal from the at least one semiconductor element,

one or more electrical connection pads distinct from the device substrate, the one or more electrical connection pads being arranged on the bottom surface of the device substrate, the one or more electrical connection pads having a first height; and

at least one thermal pad distinct from the device substrate, the at least one thermal pad being arranged on the bottom surface of the device substrate, the at least one thermal pad having a second height that is larger than the first height of the one or more electrical connection pads, wherein the surface mountable semiconductor device is surface mountable through an electrical connection through a bottom of the one or more electrical connection pads;

wherein:

the at least one thermal pad is separated from the one or more electrical connection pads by a trench or gap;

the electrically conductive layer and the dielectric layer are not present or removed underneath the at least one thermal pad of the device and underneath at least part of the trench or the gap;

the at least one thermal pad being thermally connected by a thermal interconnect layer to the metallic plate or metallic core layer and the one or more electrical connection pads being electrically connected by an electrical interconnect layer to the electrically conductive layer; and

the thermal interconnect layer to the metallic plate or metallic core layer has a surface for the at least one thermal pad at the level of the surface of the electrically conductive layer facing the surface mountable semiconductor device.

14. A method of forming a surface mountable semiconductor device, the method comprising:

providing at least one semiconductor element mounted on or integrated in a device substrate, the device substrate having a top surface and a bottom surface, the top surface being proximate to the at least one semiconductor element and the bottom surface being distal from the at least one semiconductor element; and

forming one or more electrical connection pads of a first height and at least one thermal pad of a second height on the bottom surface of the device substrate such that the surface mountable semiconductor device is surface mountable through an electrical connection through a bottom of the one or more electrical connection pads, the second height of the at least one thermal pad being larger than the first height of the one or more electrical connection pads, the one or more electrical connection pads and the at least one thermal pad being distinct from the device substrate;

wherein:

the at least one thermal pad is separated from the one or more electrical connection pads by a trench or gap;

a difference in height of the first height and the second height equals a sum of thicknesses of a dielectric layer on a carrier substrate and an electrically conductive layer on the dielectric layer, or a thermal interconnect layer to a metallic plate or metallic core layer of the carrier substrate has a surface for the at least one thermal pad at the level of the surface of the dielectric layer facing the surface mountable semiconductor device.

15. The method of claim 14 wherein forming one or more electrical connection pads of a first height and at least one thermal pad of a second height on the bottom surface of the device substrate comprises plating the one or more electrical connection pads and the at least one thermal pad.

16. The method of claim 15 wherein the one or more electrical connection pads and the at least one thermal pad are copper.

17. The method of claim 14 wherein said forming one or more electrical connection pads of a first height and at least one thermal pad of a second height on the bottom surface of the device substrate occurs at a wafer level when the surface mountable semiconductor device is attached to a wafer of semiconductor devices.