Dummy memory erase or program method protected against detection
View Patent ↗In a general aspect, a method of writing data in a nonvolatile memory can include performing a first erase or program cycle to write regular data in a first memory cell of the non-volatile memory by (i) applying at least one erase or program pulse to the first memory cell and (ii) determining the state, erased or programmed, of the first memory cell, and repeating (i) and (ii) if the first memory cell is not in the desired state. The method can also include applying a predetermined number of erase or program pulses to write fake data in a second memory cell.
1. A method for writing data in a nonvolatile memory, the method comprising:
writing regular data associated with at least one calculation of a cryptographic operation in a first memory cell using a first data writing process, the writing regular data using the first data writing process including:
applying at least one erase pulse or at least one programming pulse to the first memory cell;
verifying a state of the first memory cell;
updating a count of a number of erase pulses or programming pulses applied to the first memory cell; and
if the first memory cell is not in a desired state, repeatedly applying at least one erase pulse or at least one programming pulse, verifying the state of the first memory cell and updating the count of the number of erase pulses or programming pulses applied to the first memory cell; and
writing fake data not associated with a calculation of the cryptographic operation in a second memory cell using a second data writing process, the writing fake data using the second data writing process including applying a number of erase pulses or programming pulses to the second memory cell, the number of erase pulses or programming pulses applied to the second memory cell being based on the count of the number of erase pulses or programming pulses applied to the first memory cell, regardless of a programmed state or an erased state of the second memory cell.
2. The method of claim 1 , wherein the second data writing process includes, after applying one erase pulse or programming pulse of the number of erase pulses or programming pulses to the second memory cell, performing a verification of the programmed or erased state of the second memory cell, so as to resemble the first data writing process in terms of a number of operations performed.
3. The method of claim 2 , wherein the first data writing process and the second data writing process both further include verifying whether the first data writing process or the second data writing process is being performed to determine whether to repeatedly apply at least one erase pulse or at least one programming pulse, verify the state of a respective memory cell and update the count of the number of erase pulses or programming pulses applied.
4. The method of claim 1 , wherein the first data writing process further includes storing the number of erase pulses or programming pulses applied to the first memory cell to set the first memory cell in the desired state.
5. The method according to claim 1 , wherein:
the first data writing process is performed on a plurality of memory cells; and
determining the number of erase pulses or programming pulses applied to the second memory cell includes at least one of:
determining the number of erase pulses or programming pulses applied to the second memory cell as a function of the number of erase pulses or programming pulses applied to the first memory cell using the first data writing process;
determining the number of erase pulses or programming pulses applied to the second memory cell as a function of an average number of the number of erase pulses or programming pulses applied to the plurality of memory cells using the first data writing process; and
determining the number of erase pulses or programming pulses applied to the second memory cell as a function of a maximum value of the number of erase pulses or programming pulses applied to the plurality of memory cells using the first data writing process.
6. A nonvolatile memory comprising:
an array of memory cells, and
a control circuit configured to:
write regular data associated with at least one calculation of a cryptographic operation in a first memory cell using a first data writing process, the writing regular data using the first data writing process including:
applying at least one erase pulse or at least one programming pulse to the first memory cell;
verifying a state of the first memory cell;
updating a count of a number of erase pulses or programming pulses applied to the first memory cell; and
if the first memory cell is not in a desired state, repeatedly applying at least one erase pulse or at least one programming pulse, verifying the state of the first memory cell and updating the count of the number of erase pulses or programming pulses applied to the first memory cell; and
write fake data not associated with a calculation of the cryptographic operation in a second memory cell using a second data writing process, the writing fake data using the second data writing process including applying a number of erase pulses or programming pulses to the second memory cell, the number of erase pulses or programming pulses applied to the second memory cell being based on the count of the number of erase pulses or programming pulses applied to the first memory cell, regardless of a programmed or erased state of the second memory cell.
7. The nonvolatile memory of claim 6 , wherein the control circuit, when performing the second data writing process, is further configured to, after applying one erase or program pulse of the number of erase pulses or programming pulses to the second memory cell, perform a verification of the programmed state or the erased state of the second memory cell, so as to resemble the first data writing process in terms of a number of operations performed.
8. The nonvolatile memory of claim 6 , wherein the control circuit, when performing both the first data writing process and the second data writing process, is further configured to verify whether the first data writing process or the second data writing process is being performed to determine whether to repeatedly apply at least one erase pulse or at least one programming pulse, verify the state of a respective memory cell and update the count of the number of erase pulses or programming pulses applied.
9. Nonvolatile memory according to claim 6 , wherein the control circuit is further configured to store the number of erase pulses or programming pulses applied to the first memory cell to set the first memory cell in the desired state.
10. Nonvolatile memory according to claim 6 , wherein the control circuit is further configured to:
perform the first data writing process on a plurality of memory cells; and
determine the number of erase pulses or programming pulses applied to the second memory cell by at least one of:
determining the number of erase pulses or programming pulses applied to the second memory cell as a function of the number of erase pulses or programming pulses applied to the first memory cell using the first data writing process;
determining the number of erase pulses or programming pulses applied to the second memory cell as a function of an average number of the number of erase pulses or programming pulses applied to the plurality of memory cells using the first data writing process; and
determining the number of erase pulses or programming pulses applied to the second memory cell as a function of a maximum value of the number of erase pulses or programming pulses applied to the plurality of memory cells using the first data writing process.
11. The nonvolatile memory of claim 6 , wherein the control circuit is configured to:
memorize an address of the second memory cell, and
based on the memorized address, only apply the second data writing process to the second memory cell.
12. The nonvolatile memory of claim 6 , wherein the nonvolatile memory is included in a mobile electronic device.