IP Library Granted Patent US 9,882,007
Granted Patent B2
US 9,882,007 · App. 14/409,867 · Granted Jan 30, 2018

Handle for semiconductor-on-diamond wafers and method of manufacture

Inventors: Quentin Diduck (Santa Clara, CA); Daniel Francis (Santa Clara, CA); Frank Yantis Lowe (Santa Clara, CA); Felix Ejeckham (Santa Clara, CA)
Assignee: RFHIC Corporation
H01L29/1602H01L21/02002H01L21/2007H01L21/6835H01L23/3732H01L24/29H01L24/98H01L29/165H01L2221/6835H01L2221/68318H01L2221/68381H01L2924/0002Y10T428/24355
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Quick Facts
Patent No.
US 9,882,007
App. No.
14/409,867
Granted
Jan 30, 2018
Kind
B2
Abstract

Methods for mounting and dismounting thin and/or bowed semiconductor-on-diamond wafers ( 401 ) to a carrier ( 407 ) are disclosed that flatten said wafers and provide mechanical support to enable efficient semiconductor device processing on said semiconductor-on-diamond wafers.

Claims (28)

1. A composite wafer comprising:

a semiconductor-on-diamond wafer comprising at least one layer of single-crystal semiconductor and at least one layer of diamond;

a carrier plate that includes diamond material; and

an adhesive disposed between said semiconductor-on-diamond wafer and said carrier plate;

wherein said at least one layer of diamond is proximal to said carrier plate,

wherein said carrier plate comprises a material having a coefficient of linear thermal expansion a at 20° C. in at least one plane of no more than 10.0×10 −6 K −1 ,

wherein said adhesive comprises a material having a melting point higher than 1000° C.,

wherein said adhesive is capable of withstanding a temperature change of at least 900° C. in no more than 1.5 minutes while maintaining bonding between the semiconductor-on-diamond wafer and the carrier plate,

wherein an exposed surface of single-crystal semiconductor has a surface flatness of lower than 30 μm over a total area of the exposed surface of single-crystal semiconductor,

wherein the composite wafer has a bow of no more than 30 μm over the total area of the composite wafer,

wherein the composite wafer has a thickness variation of no more than 30 μm over the total area of the composite wafer,

wherein the composite wafer has a longest linear dimension of at least 120 mm, and

wherein said at least one layer of single-crystal semiconductor comprises at least one semiconductor selected from the group containing gallium nitride, aluminum nitride, and indium nitride.

2. A composite wafer according to claim 1 , wherein the coefficient of linear thermal expansion a at 20° C. of the material of said carrier plate is no more than 8.0×10 −6 K −1 .

3. A composite wafer according to claim 1 , wherein said carrier plate is formed of a diamond composite material or a CVD diamond wafer.

4. A composite wafer according to claim 1 , wherein said adhesive is porous.

5. A composite wafer according to claim 1 , wherein said adhesive comprises a material having a coefficient of linear thermal expansion a at 20° C. in at least one plane of no more than 10.0×10-6 K-1.

6. A composite wafer according to claim 1 , wherein the melting point of the material of said adhesive is at least 1400° C.

7. A composite wafer according to claim 1 , wherein said adhesive is chemical resistant to one, more, or all of: HF; HCl; H 2 SO 4 ; HNO 3 ; KOH; H 2 O 2 ; Tetramethylammonium hydroxide (TMAH); Acetone; Isopropyl Alcohol (IPA); Methanol; Methylene Chloride; N-Methyl-2-pyrrolidone (NMP, 1165); Methyl Isobutyl Ketone (MIBK); and Methyl Ethyl Ketone (MEK).

8. A composite wafer according to claim 1 , wherein said adhesive is a ceramic adhesive.

9. A composite wafer according to claim 8 , wherein said ceramic adhesive comprises boron nitride.

10. A composite wafer according to claim 1 , wherein the surface flatness of the exposed surface of single-crystal semiconductor is lower than 20 μm over a total area of the exposed surface of single-crystal semiconductor.

11. A composite wafer according to claim 1 , wherein the bow of the composite wafer is no more than 20 μm over a total area of the composite wafer.

12. A composite wafer according to claim 1 , wherein the thickness variation of the composite wafer is no more than 20 μm over the total area of the composite wafer.

13. A composite wafer according to claim 1 , wherein the composite wafer has a tilt of no more than 30 μm over the total area of the composite wafer, wherein the tilt corresponds to a variation in edge height around the composite wafer when the composite wafer is laid on a flat surface.

14. A composite wafer according to claim 1 , wherein said semiconductor-on-diamond wafer has thickness less than 200 μm and said flat carrier plate has a thickness larger than 400 μm.

15. A composite wafer according to claim 1 , wherein the adhesive has a beveled edge.

16. A composite wafer according to claim 1 , further comprising a sealant configured to seal areas on said composite wafer where said adhesive would otherwise be exposed.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY DATA PREVIOUSLY RECORDED AT REEL: 041113 FRAME: 0781. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 19, 2018
From: RFHIC CORPORATION
To: RFHIC CORPORATION; AKASH SYSTEMS, INC.
Reel/Frame 047953/0428 →
TECHNOLOGY AGREEMENT. ASSIGNMENT OF INTELLECTUAL PROPERTY FOR COMMERCIAL SATELLITE SYSTEMS, SUBSYSTEMS, MODULES AND DEVICES Recorded Jan 13, 2017
From: RFHIC CORPORATION
To: AKASH SYSTEMS, INC.
Reel/Frame 041113/0781 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2016
From: ELEMENT SIX TECHNOLOGIES US CORPORATION
To: RFHIC CORPORATION
Reel/Frame 039916/0416 →
Continuity (2)
Provisional Application 61667864 · Jul 3, 2012
Related Publication 20150200254A1 · Jul 16, 2015