Wafer level light-emitting diode array and method for manufacturing same

1. A light emitting diode array, comprising:

a growth substrate;

a plurality of light emitting diodes arranged on the substrate, each of the plurality of light emitting diodes having a first semiconductor layer, an active layer and a second semiconductor layer; and

a plurality of upper electrodes arranged on the plurality of light emitting diodes and formed of an identical material, each of the plurality of upper electrodes being electrically connected to the first semiconductor layer of a respective one of the light emitting diodes,

wherein at least one of the upper electrodes is electrically connected to the second semiconductor layer of an adjacent one of the light emitting diodes, and another of the upper electrodes is insulated from the second semiconductor layer of an adjacent one of the light emitting diodes,

wherein each of the light emitting diodes has a via hole for causing the first semiconductor layer to be exposed through the second semiconductor layer and the active layer, and

wherein each of the upper electrodes is connected to the first semiconductor layer of a respective one of the light emitting diodes through the via hole.

2. The light emitting diode array of claim 1 , wherein the upper electrodes comprise ohmic contact layers in ohmic contact with the first semiconductor layers.

3. The light emitting diode array of claim 2 , wherein the ohmic contact layers comprise any one metallic material selected from the group consisting of Cr, Ni, Ti, Rh and Al.

4. The light emitting diode array of claim 1 , wherein the ohmic contact layers comprise ITO.

5. The light emitting diode array of claim 2 , wherein the upper electrodes comprise reflective conductive layers positioned on the ohmic contact layers.

6. The light emitting diode array of claim 1 , further comprising a first interlayer insulating layers arranged between the light emitting diodes and the upper electrodes,

wherein the upper electrodes are insulated from side surfaces of the light emitting diodes by the first interlayer insulating layer.

7. The light emitting diode array of claim 6 , further comprising lower electrodes respectively arranged on the second semiconductor layers of the light emitting diodes,

wherein the first interlayer insulating layer exposes a portion of the lower electrode on each of the light emitting diodes, and

wherein the upper electrode(s) electrically connected to the second semiconductor layer of the adjacent light emitting diode is connected to the exposed portion of the lower electrode through the first interlayer insulating layer.

8. The light emitting diode array of claim 7 , wherein each of the lower electrodes comprises a reflective layer.

9. The light emitting diode array of claim 7 , further comprising a second interlayer insulating layer covering the upper electrodes,

wherein the second interlayer insulating layer exposes one of the lower electrodes and the upper electrode insulated from the second semiconductor layer of the adjacent light emitting diode.

10. The light emitting diode array of claim 9 , wherein the light emitting diodes are connected in series by the upper electrodes, and

wherein the second interlayer insulating layer exposes lower and upper electrodes corresponding to light emitting diodes at both ends of the light emitting diodes connected in series.

11. The light emitting diode array of claim 9 , further comprising first and second pads positioned on the second interlayer insulating layer, wherein the first pad is connected to the lower electrode exposed through the second interlayer insulating layer, and the second pad is connected to the upper electrode exposed through the second interlayer insulating layer.

12. The light emitting diode array of claim 1 , wherein the upper electrodes occupy at least 30% and less than 100% of the entire area of the light emitting diode array.

13. The light emitting diode array of claim 1 , wherein each of the upper electrodes is in the form of a plate or sheet having a ratio of length to width in a range of 1:3 to 3:1.

14. The light emitting diode array of claim 1 , wherein at least one of the upper electrodes has a length or width larger than that of a respective one of the light emitting diodes.

15. The light emitting diode array of claim 1 , wherein the upper electrodes comprise reflective conductive layers.

16. The light emitting diode array of claim 15 , further comprising a first interlayer insulating layers arranged between the light emitting diodes and the upper electrodes,

wherein the upper electrodes are insulated from side surfaces of the light emitting diodes by the first interlayer insulating layer.

17. The light emitting diode array of claim 16 , wherein the first interlayer insulating layer and the upper electrodes construct an omni-directional reflector.

18. The light emitting diode array of claim 16 , wherein the first interlayer insulating layer comprises a distributed Bragg reflector.

19. A method of forming a light emitting diode array, the method comprising:

forming a plurality of light emitting diodes, each of the plurality of light emitting diodes having a first semiconductor layer, an active layer and a second semiconductor layer on a growth substrate, wherein each of the plurality of light emitting diodes has the first semiconductor layer exposed by removing the second semiconductor layer and the active layer;

forming a first interlayer insulating layer for covering the light emitting diodes, wherein the first interlayer insulating layer exposes the exposed first semiconductor layers and has openings positioned on the second semiconductor layer of each of the light emitting diodes; and

forming a plurality of upper electrodes from an identical material on the first interlayer insulating layer,

wherein each of the upper electrodes is connected to the first semiconductor layer of a respective one of the light emitting diodes, and

wherein at least one of the upper electrodes is electrically connected to the second semiconductor layer of an adjacent one of the light emitting diodes through the opening of the first interlayer insulating layer, and another of the upper electrodes is insulated from the second semiconductor layer of an adjacent one of the light emitting diodes,

wherein each of the upper electrodes comprises a reflective conductive layer and the first interlayer insulating layer comprises a distributed Bragg reflector.

20. The method of claim 19 , further comprising:

forming lower electrodes on the second semiconductor layers of the respective light emitting diodes before the first interlayer insulating layer is formed.

21. The method of claim 20 , further comprising:

forming a second interlayer insulating layer on the upper electrodes,

wherein the second interlayer insulating layer exposes one of the lower electrodes and the other upper electrode insulated from the second semiconductor layer of the adjacent light emitting diode.

22. The method of claim 21 , further comprising:

forming first and second pads on the second interlayer insulating layer,

wherein the first pad is connected to the lower electrode, and the second pad is connected to the upper electrode.

23. The method of claim 19 , further comprising:

cutting the growth substrate into individual units,

wherein the upper electrodes occupy at least 30% and less than 100% of the area of the light emitting diode array of each of the cut individual units.

24. A light emitting diode array, comprising:

a growth substrate;

a plurality of light emitting diodes arranged on the substrate, each of the plurality of light emitting diodes having a first semiconductor layer, an active layer and a second semiconductor layer; and

a plurality of upper electrodes arranged on the plurality of light emitting diodes and formed of an identical material, each of the plurality of upper electrodes being electrically connected to the first semiconductor layer of a respective one of the light emitting diodes,

wherein at least one of the upper electrodes is electrically connected to the second semiconductor layer of an adjacent one of the light emitting diodes, and another of the upper electrodes is insulated from the second semiconductor layer of an adjacent one of the light emitting diodes,

wherein the light emitting diode array further comprises a first interlayer insulating layers arranged between the light emitting diodes and the upper electrodes, wherein the upper electrodes are insulated from side surfaces of the light emitting diodes by the first interlayer insulating layer,

wherein the light emitting diode array further comprises lower electrodes respectively arranged on the second semiconductor layers of the light emitting diodes, wherein the first interlayer insulating layer exposes a portion of the lower electrode on each of the light emitting diodes, and wherein the upper electrode(s) electrically connected to the second semiconductor layer of the adjacent light emitting diode is connected to the exposed portion of the lower electrode through the first interlayer insulating layer,

wherein the light emitting diode array further comprises a second interlayer insulating layer covering the upper electrodes, wherein the second interlayer insulating layer exposes one of the lower electrodes and the upper electrode insulated from the second semiconductor layer of the adjacent light emitting diode, and

wherein the light emitting diode array further comprises first and second pads positioned on the second interlayer insulating layer, wherein the first pad is connected to the lower electrode exposed through the second interlayer insulating layer, and the second pad is connected to the upper electrode exposed through the second interlayer insulating layer.

25. A light emitting diode array, comprising:

a growth substrate;

a plurality of light emitting diodes arranged on the substrate, each of the plurality of light emitting diodes having a first semiconductor layer, an active layer and a second semiconductor layer; and

a plurality of upper electrodes arranged on the plurality of light emitting diodes and formed of an identical material, each of the plurality of upper electrodes being electrically connected to the first semiconductor layer of a respective one of the light emitting diodes,

wherein at least one of the upper electrodes is electrically connected to the second semiconductor layer of an adjacent one of the light emitting diodes, and another of the upper electrodes is insulated from the second semiconductor layer of an adjacent one of the light emitting diodes,

wherein the upper electrodes comprise reflective conductive layers,

wherein the light emitting diode array further comprises a first interlayer insulating layers arranged between the light emitting diodes and the upper electrodes,

wherein the upper electrodes are insulated from side surfaces of the light emitting diodes by the first interlayer insulating layer, and

wherein the first interlayer insulating layer comprises a distributed Bragg reflector.

26. A method of forming a light emitting diode array, the method comprising:

forming a plurality of light emitting diodes, each of the plurality of light emitting diodes having a first semiconductor layer, an active layer and a second semiconductor layer on a growth substrate, wherein each of the plurality of light emitting diodes has the first semiconductor layer exposed by removing the second semiconductor layer and the active layer;

forming a first interlayer insulating layer for covering the light emitting diodes, wherein the first interlayer insulating layer exposes the exposed first semiconductor layers and has openings positioned on the second semiconductor layer of each of the light emitting diodes; and

forming a plurality of upper electrodes from an identical material on the first interlayer insulating layer,

wherein each of the upper electrodes is connected to the first semiconductor layer of a respective one of the light emitting diodes, and

wherein at least one of the upper electrodes is electrically connected to the second semiconductor layer of an adjacent one of the light emitting diodes through the opening of the first interlayer insulating layer, and another of the upper electrodes is insulated from the second semiconductor layer of an adjacent one of the light emitting diodes,

wherein the method further comprises forming lower electrodes on the second semiconductor layers of the respective light emitting diodes before the first interlayer insulating layer is formed,

wherein the method further comprises forming a second interlayer insulating layer on the upper electrodes, wherein the second interlayer insulating layer exposes one of the lower electrodes and the other upper electrode insulated from the second semiconductor layer of the adjacent light emitting diode, and

wherein the method further comprising forming first and second pads on the second interlayer insulating layer, wherein the first pad is connected to the lower electrode, and the second pad is connected to the upper electrode.