Protection against side channels
View Patent ↗The description pertains in particular to a method of protecting an electronic device (SCARD), when the electronic device implements a cryptographic algorithm (AES), against side channel attacks. The cryptographic algorithm (AES) operating on an array of states which forms the subject of a secure processing. The description relates also to an electronic device (SCARD), a computer program and a storage medium for the implementation of such a method.
1. A protection method for protecting an electronic device (SCARD), when the electronic device implements a cryptographic algorithm (AES), against side channel attacks, the cryptographic algorithm (AES) working with a state array (MAT1, MAT2, MAT3), the cryptographic algorithm (AES) being designed to generate (SHFT_R), from a current state array (MAT1), a second state array (MAT2) in which each row is obtained by shifting the corresponding row of the current state array (MAT1), then to generate (MIX_C), from the second state array (MAT2), a third state array (MAT3) in which the elements of each column are the result of mixing elements of the corresponding column of the second state array (MAT2), wherein the method comprises replacing said two consecutive generations (SHFT_R, MIX_C) of the respective second and third state array (MAT2, MAT3) by a secure generation (SEC_GEN), from the current state array (MAT1), of a state array equal to the third state array (MAT3), this secure generation (SEC_GEN) mixing, in a randomized order, the elements of the current state array (MAT1) that would have been located in a same column of the second state array (MAT2) if said second state array had been generated, in order to produce the corresponding column of the generated state array.
2. The protection method according to claim 1 , wherein each element of a state array having been identified by an index, the mixing of the elements of the current state array (MAT1) by secure generation (SEC_GEN) is based on an index conversion function that takes as its input parameter an index (i,j) of a virtual element of the second state array (MAT2) and outputs the index (ic,jc) of the corresponding element in the current state array (MAT1).
3. The protection method according to claim 1 , wherein the shift applied to a row during generation (SHFT_R) of the second state array (MAT2) is a shift of n elements, n indicating the row number, the first row being numbered n=0.
4. The protection method according to claim 1 , wherein the mixing of elements of a column of the second state array (MAT2) in order to obtain an element of the third state array (MAT3) during its generation (MIX_C) is a linear combination of these elements.
5. The protection method according to claim 4 , wherein the scalars used for the linear combination are dependent on the row where the element of the third state array (MAT3) is located.
6. The protection method according to claim 1 , wherein a shift rows operation and a mix columns operation are randomized.
7. A computer-readable non-transitory storage medium storing a set of instructions which, when executed by a processor of an electronic device, causes the processor to implement a protection method for protecting an electronic device, when the electronic device implements a cryptographic algorithm, against side channel attacks, the cryptographic algorithm working with a state array, the cryptographic algorithm being designed to generate, from a current state array, a second state array in which each row is obtained by shifting the corresponding row of the current state array, then to generate, from the second state array, a third state array in which the elements of each column are the result of mixing elements of the corresponding column of the second state array, the method comprising replacing said two consecutive generations of the respective second and third state array by a secure generation, from the current state array, of a state array equal to the third state array, this secure generation mixing, in a randomized order, the elements of the current state array that would have been located in a same column of the second state array if said second state array had been generated, in order to produce the corresponding column of the generated state array.
8. An electronic device (SCARD) arranged to implement a cryptographic algorithm (AES) working with a state array, the cryptographic algorithm (AES) being designed to generate (SHFT_R), from a current state array (MAT1), a second state array (MAT2) in which each row is obtained by shifting the corresponding row of the current state array (MAT1), then to generate (MIX_C), from the second state array (MAT2), a third state array (MAT3) in which the elements of each column are the result of mixing elements of the corresponding column of the second state array (MAT2), the electronic device (SCARD) comprising a protection circuit (MP) to protect against side channel attacks, the protection circuit (MP) being arranged to replace said two consecutive generations (SHFT_R, MIX_C) of the respective second and third state array (MAT2, MAT3) by a secure generation (SEC_GEN), from the current state array (MAT1), of a state array equal to the third state array (MAT3), this secure generation (SEC_GEN) mixing, in a randomized order, the elements of the current state array (MAT1) that would have been located in a same column of the second state array (MAT2) if said second state array had been generated, in order to produce the corresponding column of the generated state array.
9. The electronic device (SCARD) according to claim 8 , wherein, each element of a state array being identified by an index, the protection circuit (MP) is arranged to mix elements of the current state array (MAT1) by secure generation (SEC_GEN) based on an index conversion function that takes as its input parameter an index (i,j) of a virtual element of the second state array (MAT2) and outputs the index (ic,jc) of the corresponding element in the current state array (MAT1).
10. The electronic device (SCARD) according to claim 8 , wherein the shift applied to a row during generation (SHFT_R) of the second state array (MAT2) is a shift of n elements, n denoting the row number, the first row being numbered n=0.
11. The electronic device (SCARD) according to claim 8 , wherein the mixing of elements of a column of the second state array (MAT2) in order to obtain an element of the third state array (MAT3) during its generation (MIX_C) is a linear combination of these elements.
12. The electronic device (SCARD) according to claim 11 , wherein the scalars used for the linear combination are dependent on the row where the element of the third state array is located.