Load transient asynchronous boost for pulse width modulation modulator
A pulse width modulation controller (PWM) is disclosed which has a MOSFET ( 15 ) responsive to the error voltage (Verror) signal from the PWM amplifier ( 17 ) to detect a transient condition without delay ΔTd. The MOSFET drain generates and applies a detection signal (S) to a delaying circuit (D). The delaying circuit (D) is responsive to the transient detection signal (S) to asynchronously output two latch signals (S 1 ) and (S 2 ) which on application to respective latch circuits (L 1 , L 2 ) cause a change in conduction state of PMOS ( 8 ) and NMOS ( 9 ). This arrangement reduces voltage undershoot.
1. A PWM controller, comprising:
an amplifier having an output that provides an error signal;
a transient load detection circuit, which comprises
a transistor having a gate communicating with the amplifier output to be responsive to the error signal, a drain that produces a detection signal, and a source terminal, and
a source resistance in parallel with a source capacitor connected to the source terminal whereby, in steady state operation all current flows through the source resistance and when the detection signal is rapidly changing the rapid voltage change at the source induces a current flow across the source capacitor to short circuit the source resistance; and
a delaying circuit connected to the drain of the transistor to receive the detection signal, wherein the delaying circuit is responsive to the detection signal to generate first and second latch signals, which are applied, respectively to a PMOS latch and an NMOS latch, said PMOS latch and said NMOS latch being connected to, respectively, a PMOS transistor and an NMOS transistor whereby, in response to said first and second latch signals a respective conduction state of the PMOS transistor and the NMOS transistor are switched.
2. A PWM controller according to claim 1 , wherein a value of the source resistance is of the order of 1-999 MΩ.
3. A PWM controller according to claim 1 , wherein the detection circuit is arranged to generate rectangular latch signals synchronized on a step of the detection signal.
4. A PWM controller according to claim 3 , wherein the transient load detection circuit is arranged to delay generation of one of the first and second latch signals with regard to the other of the first and second latch signal to asynchronously change the respective conduction state of the PMOS and NMOS transistors.
5. A PWM controller according to claim 1 , further comprising:
a comparator coupled to the amplifier output to receive the error signal, compare the error signal to a signal from a ramp generator, and output a signal to the PMOS latch based on the comparison.
6. A PWM controller according to claim 1 , wherein the delay circuit is coupled to a clock input of the PMOS latch.
7. A PWM controller according to claim 6 , wherein an output of the PMOS latch is coupled to a clock input of the NMOS latch.
8. A PWM controller according to claim 1 , wherein a first input of the amplifier is coupled to a voltage reference an a second input of the amplifier is coupled to an output of the PWM controller.