UNIVERSAL MULTI-CHANNEL GNSS SIGNAL RECEIVER
A universal multi-channel receiver for receiving and processing signals from different navigation systems is provided. The universal receiver is implemented as an ASIC receiver with a number of universal channels. The receiver with universal channels is capable of receiving and processing signals from navigation satellites located within a direct access zone. The universal receiver has a plurality of channels that share the same memory. The universal receiver can determine its coordinates using all existing navigation systems (GPS, GLONASS and GALILEO). The universal receiver can receive and process any (PN) signals used for various purposes.
1 . A universal multi-channel receiver comprising:
an antenna for receiving a signal;
a plurality of universal channels having request generating modules (RGMs) operating at a channel frequency and generating memory codes;
a processor for controlling the plurality of universal channels and the RGMs;
a plurality of RF tracts connected to the antenna, the RF tracts providing the signal to the universal channels; and
a shared memory coupled to the processor and accessible by the universal channels for storing memory code sequences of a GNSS signal;
wherein:
the RGMs retrieve the code sequences from the shared memory at a pre-set number of memory cycles;
wherein the RGMs access the shared memory through a common response generating module;
the code sequence from the RGMs are multiplied by the RF tract signal and its carrier frequency; and
a resulting code sequence is accumulated over a time period controlled by the processor.
2 . The multi-channel receiver of claim 1 , further comprising a FIFO connected to the processor, wherein the processor writes new memory codes into the shared memory via the FIFO.
3 . The multi-channel receiver of claim 1 , wherein a new memory code sequence with its own frequency is generated by multiplying the memory code by a signal generated by an additional code generator.
4 . The multi-channel receiver of claim 3 , wherein the new memory code sequence is stored in the shared memory and is provided to the universal channels via the RGMs and the common response generating module.
5 . The multi-channel receiver of claim 1 , wherein the RGMs include remainder registers for storing remainders of the memory codes.
6 . The multi-channel receiver of claim 5 , wherein the RGMs provide, to the universal channels, the memory codes retrieved from the shared memory and from the remainder registers.
7 . The multi-channel receiver of claim 1 , wherein the memory code is divided into words.
8 . The multi-channel receiver of claim 1 , wherein a memory codes location map is stored in the shared memory and modified by the processor.
9 . The multi-channel receiver of claim 1 , wherein the signal received by the antenna is a pseudo-noise (PN) signal.
10 . The multi-channel receiver of claim 1 , further comprising a FIFO connected to the processor, and wherein the FIFO writes data into the shared memory when the request processing module has no requests from the RGMs.
11 . The multi-channel receiver of claim 1 , wherein the shared memory is a dual port memory, and the processor writes data to the dual ported memory independent of any reads from the dual ported memory.
12 . The multi-channel receiver of claim 1 , wherein the shared memory is accessed according to a processor-controlled priority.
13 . The multi-channel receiver of claim 12 , wherein the RGMs receive data from the shared memory based on priority defined by settings of the system.
14 . The method of claim 1 , wherein, when the memory code is not equal to a multiple of a width of the shared memory, a remainder is written into the RGM of the channel.
15 . The method of claim 1 , wherein the shared memory includes multiple individually addressable storage areas, but at any given time only one word can be read, the word containing N+1 samples of the reference code sequence for a particular universal channel, N+1 being a width of the shared memory.
16 . The method of claim 1 , wherein each channel receives data from the shared memory based on priority of its request.
17 . The method of claim 1 , wherein each channel receives data from the shared memory in order of its channel number.
18 . The method of claim 1 , wherein the code sequence is divided into words that are multiples of N+1 and are stored sequentially in the shared memory.
19 . The method of claim 1 , wherein the code sequence is divided into words that are not multiples of N+1 and the last word in the memory that has a width of less than N+1 is a remainder.
20 . The method of claim 1 , wherein read requests to the shared memory are blocked when the code sequence is shifted forward to speed up a code sequence, until the shift ends.