IP Library Granted Patent US 9,071,260
Granted Patent B2
US 9,071,260 · App. 14/447,050 · Granted Jun 30, 2015

Method and related device for generating a digital output signal corresponding to an analog input signal

Inventors: Mario Chiricosta (Tremestieri Etneo, IT); Calogero Marco Ippolito (Aci Castello, IT); Mario Maiore (Aci Sant'Antonio, IT); Orlando Peluso (Mascalucia, IT); Michele Vaiana (Paterno′, IT)
Assignee: STMicroelectronics S.r.l.
H03M1/0626H03M1/20H03M1/0639H03M1/12
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Quick Facts
Patent No.
US 9,071,260
App. No.
14/447,050
Granted
Jun 30, 2015
Kind
B2
Abstract

An embodiment of a circuit includes an input node, a generator, a combiner, a converter, and a filter. The input node is configured to receive an input signal in a first domain, and the generator is configured to generate a periodic signal in the first domain. The combiner is configured to combine the input and periodic signals into a resulting signal in the first domain, and the converter is configured to convert the resulting signal into a converted signal in a second domain. And the filter is configured to remove from the converted signal substantially all of a frequency component of the converted signal having substantially a same frequency as a frequency component of the periodic signal.

Claims (38)

1. A circuit, comprising:

an input node configured to receive an input signal in a first domain;

a generator configured to generate a periodic signal in the first domain, said periodic signal having a main frequency and first tones which are harmonics of the main frequency;

a combiner configured to combine the input and periodic signals into a resulting signal in the first domain;

a converter configured to sample the resulting signal at a sampling frequency and convert the sampled resulting signal into a converted signal in a second domain; and

a filter having a frequency response including zeroes at a plurality of second tones with passbands between adjacent second tones, said filter configured to remove frequency components of the periodic signal from the converted signal;

wherein the main frequency is equal to an integer fraction of the sampling frequency of the converter and the harmonic first tones of the periodic signal are centered on ones of the second tones for the zeroes of the frequency response.

2. The circuit of claim 1 wherein:

the first domain is an analog domain; and

the second domain is a digital domain.

3. The circuit of claim 1 wherein:

the first domain is a digital analog domain; and

the second domain is an analog domain.

4. The circuit of claim 1 wherein the periodic signal is a sinusoid.

5. The circuit of claim 1 wherein the periodic signal is a triangle wave.

6. The circuit of claim 1 wherein the periodic signal is a square wave.

7. The circuit of claim 1 wherein the combiner is an adder.

8. The circuit of claim 1 wherein the converter is a digital-to-analog converter.

9. The circuit of claim 1 wherein the converter is an analog-to-digital converter.

10. The circuit of claim 1 wherein the filter is a finite-impulse-response filter.

11. A system, comprising:

a first integrated circuit including

an input node configured to receive an input signal in a first domain,

a generator configured to generate a periodic signal in the first domain, said periodic signal having a main frequency and first tones which are harmonics of the main frequency,

a combiner configured to combine the input and periodic signals into a resulting signal in the first domain,

a converter configured to sample the resulting signal at a sampling frequency and convert the sampled resulting signal into a converted signal in a second domain, and

a filter having a frequency response including zeroes at a plurality of second tones with passbands between adjacent second tones, said filter configured to remove frequency components of the periodic signal from the converted signal;

wherein the main frequency is equal to an integer fraction of the sampling frequency of the converter and the harmonic first tones of the periodic signal are centered on ones of the second tones for the zeroes of the frequency response; and

a second integrated circuit coupled to the first integrated circuit.

12. The system of claim 11 wherein the first and second integrated circuits are disposed on a same integrated-circuit die.

13. The system of claim 11 wherein the first and second integrated circuits are disposed on respective integrated-circuit dies.

14. The system of claim 11 wherein one of the first and second integrated circuits includes a computing circuit.

15. A method, comprising:

generating an output signal in a first domain in response to a first input signal and a periodic second input signal, said periodic second input signal having a main frequency and first tones which are harmonics of the main frequency;

converting the output signal from the first domain to a second domain by sampling the output signal at a sampling frequency; and

removing frequency components of the periodic second input signal from the converted output signal by filtering with a filter having a frequency response including zeroes at a plurality of second tones with passbands between adjacent second tones;

wherein the main frequency is equal to an integer fraction of the sampling frequency and the harmonic first tones of the periodic second input signal are centered on ones of the second tones for the zeroes of the frequency response.

16. The method of claim 15 wherein generating the output signal includes superimposing one of the first and second input signals on the other of the first and second input signals.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2022
From: STMICROELECTRONICS S.R.L.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 061828/0243 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2014
From: CHIRICOSTA, MARIO; IPPOLITO, CALOGERO MARCO; MAIORE, MARIO; PELUSO, ORLANDO; VAIANA, MICHELE
To: STMICROELECTRONICS S.R.L.
Reel/Frame 033431/0001 →
Priority Claims (1)
IT M12013A1273 · Jul 30, 2013 · national
Continuity (1)
Related Publication 20150035691A1 · Feb 5, 2015