Per IO direct memory access redirection
View Patent ↗A bridge device tracks each individual IO between two PCIe busses and provides a translated address based on a scatter/gather list. Tracking provides a natural means of scatter/gather list translation to and from a native PCIe storage protocol's scatter/gather list (or other scatter/gather like mechanism). In addition, the awareness of the IO context provides a means for detecting erroneous transactions that would otherwise cause a system error and/or data corruption to be aborted preventing those error scenarios.
1. A bridge apparatus comprising:
a processor;
one or more host ports connected to the processor;
one or more device ports connected to the processor; and
memory in communication with the processor,
wherein the processor is configured to:
receive a transaction request;
determine a device interface protocol selected from one of advanced host controller interface (AHCI), nonvolatile memory express (NVME), and small computer system interface over peripheral component interconnect express (SOP);
initiate a device communication process according to the determined device interface;
produce a scatter/gather list based on and unique to the transaction request, the scatter/gather list including a memory space type and associating one or more host memory addresses in the host memory address space with one or more memory address offsets and transaction sizes; and
inform a direct memory access redirector that a message identifier is associated with a requestor of the transaction request.
2. The bridge apparatus of claim 1 , wherein the processor is further configured to determine a data transfer size based on the transaction request and wherein the memory space type included in the scatter/gather list specifies a host port from among the one or more host ports.
3. The bridge apparatus of claim 1 , wherein the processor is further configured to provide a memory address range in the device memory space.
4. The bridge apparatus of claim 3 , wherein the processor is further configured to dynamically translate one or more device side memory addresses to one or more host side memory addresses.
5. The bridge apparatus of claim 3 , wherein the processor is further configured to dynamically translate one or more device side memory addresses to one or more memory addresses in the memory.
6. The bridge apparatus of claim 5 , wherein the processor is further configured to pass the transaction request from one of the one or more host ports to one of the one or more device ports.
7. A memory device controller comprising:
a processor;
memory connected to the processor; and
computer executable program code configured to execute on the processor,
wherein the computer executable program code is configured to:
receive a transaction request;
determine a device interface protocol selected from one of advanced host controller interface (AHCI), nonvolatile memory express (NVME), and small computer system interface over peripheral component interconnect express (SOP);
initiate a device communication process according to the determined device interface;
produce a scatter/gather list based on the transaction request, the scatter/gather list specifying a memory space type for the transaction request and associating one or more host memory addresses in the host memory address space with one or more memory address offsets and transaction sizes;
inform a direct memory access redirector that a message identifier is associated with a requestor of the transaction request.
8. The memory device controller of claim 7 , wherein the computer executable program code is further configured to determine a data transfer size based on the transaction request and wherein the memory space type included in the scatter/gather list specifies a use of internal memory.
9. The memory device controller of claim 7 , wherein the computer executable program code is further configured to provide a memory address range in the device memory space.
10. The memory device controller of claim 9 , wherein the computer executable program code is further configured to dynamically translate one or more device side memory addresses to one or more host side memory addresses.
11. The memory device controller of claim 9 , wherein the computer executable program code is further configured to dynamically translate one or more device side memory addresses to one or more memory addresses in the memory.
12. The memory device controller of claim 11 , wherein the computer executable program code is further configured to pass the transaction request to a host device.
13. A data storage system comprising:
a memory device controller comprising:
a processor; and
memory in communication with the processor; and one or more data storage devices,
wherein:
the processor is configured to:
receive a transaction request;
determine a device interface protocol selected from one of advanced host controller interface (AHCI), nonvolatile memory express (NVME), and small computer system interface over peripheral component interconnect express (SOP);
initiate a device communication process according to the determined device interface;
produce a scatter/gather list based on the transaction request, the scatter/gather list specifying a memory space type for the transaction request and associating one or more host memory addresses in the host memory address space with one or more memory address offsets and transaction sizes;
inform a direct memory access redirector that a message identifier is associated with a requestor of the transaction request.
14. The system of claim 13 , wherein the one or more data storage devices are peripheral component interconnect express devices.
15. The system of claim 13 , wherein the processor is further configured to determine a data transfer size based on the transaction request and wherein the memory space type included in the scatter/gather list specifies a host port.
16. The system of claim 13 , wherein the processor is further configured to provide a memory address range in the device memory space.
17. The system of claim 16 , wherein the processor is further configured to dynamically translate one or more device side memory addresses to one or more host side memory addresses.
18. The system of claim 13 , wherein the processor is further configured to dynamically translate one or more device side memory addresses to one or more memory addresses in the memory.
19. The system of claim 18 , wherein the processor is further configured to provide a memory address range in the device memory space to a host device.
20. The system of claim 19 , wherein the processor is further configured to pass a data transfer request from the host device to one of the one or more data storage devices.