Method and apparatus for memory power and/or area reduction
View Patent ↗A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage V mem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.
1. A system comprising:
an electronic device comprising power supply, one or more memory cells, and digital circuitry other than said one or more memory cells, wherein:
said digital circuitry other than said one or more memory cells is powered via a first supply voltage generated by said power supply;
said one or more memory cells are powered via a second supply voltage generated by said power supply;
said power supply is operable to:
control said first supply voltage independent of said second supply voltage; and
adjust said second supply voltage based on a type of data stored in said one or more memory cells;
said one or more memory cells are a first one or more memory cells; and
said system also comprises a second one or more memory cells powered via a third supply voltage generated by said power supply.
2. The system of claim 1 , wherein a first type of said data adheres to a first communication standard and a second type of data adheres to a second communication standard.
3. The system of claim 1 , wherein said first type of said data is of a first format and a second type of data is of a second format.
4. The system of claim 1 , wherein said power supply is operable to adjust said second supply voltage based on a tolerable error rate for data stored in said one or more memory cells.
5. The system of claim 1 , wherein said power supply is operable to control said third supply voltage independent of said second supply voltage and independent of said first supply voltage.
6. The system of claim 1 , wherein:
said first one or more memory cells hold a corresponding one or more most significant bits of a data word; and
said second one or more memory cells hold a corresponding one or more least significant bits of said data word.
7. The system of claim 6 , wherein cell size of said first one or more memory cells is the same as cell size of said second one or more memory cells.
8. The system of claim 7 , wherein said second supply voltage is higher than said third supply voltage.
9. The system of claim 6 , wherein cell size of said first one or more memory cells is larger than cell size of said second one or more memory cells.
10. The system of claim 9 , wherein said second supply voltage is equal to said third supply voltage.
11. The system of claim 1 , wherein:
said first one or more memory cells hold a corresponding one or more bits of a data word having a first fault sensitivity coefficient; and
said second one or more memory cells hold a corresponding one or more bits of said data word having a second fault sensitivity coefficient.
12. The system of claim 11 , wherein cell size of said first one or more memory cells is the same as cell size of said second one or more memory cells.
13. The system of claim 12 , wherein said second supply voltage is higher than said third supply voltage.
14. The system of claim 11 , wherein cell size of said first one or more memory cells is larger than cell size of said second one or more memory cells.
15. The system of claim 1 , wherein said second supply voltage is equal to said third supply voltage.
16. The system of claim 1 , wherein each of said one or more memory cells comprises cross-coupled inverters.
17. The system of claim 16 , wherein said first supply voltage is applied to source nodes of PMOS transistors of each one of said cross-coupled inverters.
18. The system of claim 1 , wherein said adjustment results in said second supply voltage being a first voltage when a first type of data is stored in said one or more memory cells and said second supply voltage being a second voltage when a second type of data is stored in said one or more memory cells.
19. The system of claim 1 , wherein said second supply voltage is applied to a source node of one or more access transistors that provide power to said one or more memory cells.
20. A system comprising:
an electronic device comprising a power supply, one or more memory cells, and digital circuitry other than said one or more memory cells, wherein:
said digital circuitry other than said one or more memory cells is powered via a first supply voltage generated by said power supply;
said one or more memory cells are powered via a second supply voltage generated by said power supply;
said power supply is operable to:
control said first supply voltage independent of said second supply voltage; and
adjust said second supply voltage based on a type of data stored in said one or more memory cells;
each of said one or more memory cells comprises cross-coupled inverters; and
said first supply voltage is applied to source nodes of PMOS transistors of each one of said cross-coupled inverters.
21. The system of claim 20 , wherein a first type of said data adheres to a first communication standard and a second type of data adheres to a second communication standard.
22. The system of claim 20 , wherein said first type of said data is of a first format and a second type of data is of a second format.
23. The system of claim 20 , wherein said power supply is operable to adjust said second supply voltage based on a tolerable error rate for data stored in said one or more memory cells.
24. The system of claim 20 , wherein:
said one or more memory cells are a first one or more memory cells;
said system also comprises a second one or more memory cells powered via a third supply voltage generated by said power supply; and
said power supply is operable to control said third supply voltage independent of said second supply voltage and independent of said first supply voltage.
25. The system of claim 20 , wherein:
said one or more memory cells are a first one or more memory cells;
said system also comprises a second one or more memory cells powered via a third supply voltage generated by said power supply;
said first one or more memory cells hold a corresponding one or more most significant bits of a data word; and
said second one or more memory cells hold a corresponding one or more least significant bits of said data word.
26. The system of claim 25 , wherein cell size of said first one or more memory cells is the same as cell size of said second one or more memory cells.
27. The system of claim 26 , wherein said second supply voltage is higher than said third supply voltage.
28. The system of claim 25 , wherein cell size of said first one or more memory cells is larger than cell size of said second one or more memory cells.
29. The system of claim 28 , wherein said second supply voltage is equal to said third supply voltage.
30. The system of claim 20 , wherein:
said one or more memory cells are a first one or more memory cells;
said system also comprises a second one or more memory cells powered via a third supply voltage generated by said power supply;
said first one or more memory cells hold a corresponding one or more bits of a data word having a first fault sensitivity coefficient; and
said second one or more memory cells hold a corresponding one or more bits of said data word having a second fault sensitivity coefficient.
31. The system of claim 30 , wherein cell size of said first one or more memory cells is the same as cell size of said second one or more memory cells.
32. The system of claim 31 , wherein said second supply voltage is higher than said third supply voltage.
33. The system of claim 30 , wherein cell size of said first one or more memory cells is larger than cell size of said second one or more memory cells.
34. The system of claim 20 , wherein:
said one or more memory cells are a first one or more memory cells;
said system also comprises a second one or more memory cells powered via a third supply voltage generated by said power supply; and
said second supply voltage is equal to said third supply voltage.
35. The system of claim 20 , wherein said adjustment results in said second supply voltage being a first voltage when a first type of data is stored in said one or more memory cells and said second supply voltage being a second voltage when a second type of data is stored in said one or more memory cells.
36. The system of claim 20 , wherein said second supply voltage is applied to a source node of one or more access transistors that provide power to said one or more memory cells.
37. A system comprising:
an electronic device comprising power supply, one or more memory cells, and digital circuitry other than said one or more memory cells, wherein:
said digital circuitry other than said one or more memory cells is powered via a first supply voltage generated by said power supply;
said one or more memory cells are powered via a second supply voltage generated by said power supply;
said power supply is operable to:
control said first supply voltage independent of said second supply voltage; and
adjust said second supply voltage based on a type of data stored in said one or more memory cells;
said adjustment results in said second supply voltage being a first voltage when a first type of data is stored in said one or more memory cells and said second supply voltage being a second voltage when a second type of data is stored in said one or more memory cells.
38. The system of claim 37 , wherein a first type of said data adheres to a first communication standard and said second type of data adheres to a second communication standard.
39. The system of claim 37 , wherein said first type of said data is of a first format and said second type of data is of a second format.
40. The system of claim 37 , wherein said power supply is operable to adjust said second supply voltage based on a tolerable error rate for data stored in said one or more memory cells.
41. The system of claim 37 , wherein:
said one or more memory cells are a first one or more memory cells;
said system also comprises a second one or more memory cells powered via a third supply voltage generated by said power supply; and
said power supply is operable to control said third supply voltage independent of said second supply voltage and independent of said first supply voltage.
42. The system of claim 37 , wherein:
said one or more memory cells are a first one or more memory cells;
said system also comprises a second one or more memory cells powered via a third supply voltage generated by said power supply;
said first one or more memory cells hold a corresponding one or more most significant bits of a data word; and
said second one or more memory cells hold a corresponding one or more least significant bits of said data word.
43. The system of claim 42 , wherein cell size of said first one or more memory cells is the same as cell size of said second one or more memory cells.
44. The system of claim 43 , wherein said second supply voltage is higher than said third supply voltage.
45. The system of claim 42 , wherein cell size of said first one or more memory cells is larger than cell size of said second one or more memory cells.
46. The system of claim 45 , wherein said second supply voltage is equal to said third supply voltage.
47. The system of claim 37 , wherein:
said one or more memory cells are a first one or more memory cells;
said system also comprises a second one or more memory cells powered via a third supply voltage generated by said power supply;
said first one or more memory cells hold a corresponding one or more bits of a data word having a first fault sensitivity coefficient; and
said second one or more memory cells hold a corresponding one or more bits of said data word having a second fault sensitivity coefficient.
48. The system of claim 47 , wherein cell size of said first one or more memory cells is the same as cell size of said second one or more memory cells.
49. The system of claim 48 , wherein said second supply voltage is higher than said third supply voltage.
50. The system of claim 47 , wherein cell size of said first one or more memory cells is larger than cell size of said second one or more memory cells.
51. The system of claim 37 , wherein:
said one or more memory cells are a first one or more memory cells;
said system also comprises a second one or more memory cells powered via a third supply voltage generated by said power supply; and
said second supply voltage is equal to said third supply voltage.
52. The system of claim 37 , wherein:
each of said one or more memory cells comprises cross-coupled inverters; and
said first supply voltage is applied to source nodes of PMOS transistors of each one of said cross-coupled inverters.
53. The system of claim 37 , wherein said second supply voltage is applied to a source node of one or more access transistors that provide power to said one or more memory cells.
54. A system comprising:
an electronic device comprising power supply, one or more memory cells, and digital circuitry other than said one or more memory cells, wherein:
said digital circuitry other than said one or more memory cells is powered via a first supply voltage generated by said power supply;
said one or more memory cells are powered via a second supply voltage generated by said power supply;
said power supply is operable to:
control said first supply voltage independent of said second supply voltage; and
adjust said second supply voltage based on a type of data stored in said one or more memory cells; and
said second supply voltage is applied to a source node of one or more access transistors that provide power to said one or more memory cells.
55. The system of claim 54 , wherein a first type of said data adheres to a first communication standard and a second type of data adheres to a second communication standard.
56. The system of claim 54 , wherein said first type of said data is of a first format and a second type of data is of a second format.
57. The system of claim 54 , wherein said power supply is operable to adjust said second supply voltage based on a tolerable error rate for data stored in said one or more memory cells.
58. The system of claim 54 , wherein:
said one or more memory cells are a first one or more memory cells;
said system also comprises a second one or more memory cells powered via a third supply voltage generated by said power supply; and
said power supply is operable to control said third supply voltage independent of said second supply voltage and independent of said first supply voltage.
59. The system of claim 54 , wherein:
said one or more memory cells are a first one or more memory cells;
said system also comprises a second one or more memory cells powered via a third supply voltage generated by said power supply;
said first one or more memory cells hold a corresponding one or more most significant bits of a data word; and
said second one or more memory cells hold a corresponding one or more least significant bits of said data word.
60. The system of claim 59 , wherein cell size of said first one or more memory cells is the same as cell size of said second one or more memory cells.
61. The system of claim 60 , wherein said second supply voltage is higher than said third supply voltage.
62. The system of claim 59 , wherein cell size of said first one or more memory cells is larger than cell size of said second one or more memory cells.
63. The system of claim 62 , wherein said second supply voltage is equal to said third supply voltage.
64. The system of claim 54 , wherein:
said one or more memory cells are a first one or more memory cells;
said system also comprises a second one or more memory cells powered via a third supply voltage generated by said power supply;
said first one or more memory cells hold a corresponding one or more bits of a data word having a first fault sensitivity coefficient; and
said second one or more memory cells hold a corresponding one or more bits of said data word having a second fault sensitivity coefficient.
65. The system of claim 64 , wherein cell size of said first one or more memory cells is the same as cell size of said second one or more memory cells.
66. The system of claim 65 , wherein said second supply voltage is higher than said third supply voltage.
67. The system of claim 64 , wherein cell size of said first one or more memory cells is larger than cell size of said second one or more memory cells.
68. The system of claim 54 , wherein:
said one or more memory cells are a first one or more memory cells;
said system also comprises a second one or more memory cells powered via a third supply voltage generated by said power supply; and
said second supply voltage is equal to said third supply voltage.
69. The system of claim 54 , wherein:
each of said one or more memory cells comprises cross-coupled inverters; and
said first supply voltage is applied to source nodes of PMOS transistors of each one of said cross-coupled inverters.
70. A system comprising:
an electronic device comprising a power supply, one or more memory cells, and digital circuitry other than said one or more memory cells, wherein:
said digital circuitry other than said one or more memory cells is powered via a first supply voltage generated by said power supply;
said one or more memory cells are powered via a second supply voltage generated by said power supply;
said power supply is operable to:
control said first supply voltage independent of said second supply voltage; and
adjust said second supply voltage based on a type of data stored in said one or more memory cells;
each of said one or more memory cells comprises cross-coupled inverters;
said one or more memory cells are a first one or more memory cells;
said system also comprises a second one or more memory cells powered via a third supply voltage generated by said power supply; and
said power supply is operable to control said third supply voltage independent of said second supply voltage and independent of said first supply voltage.
71. A system comprising:
an electronic device comprising a power supply, one or more memory cells, and digital circuitry other than said one or more memory cells, wherein:
said digital circuitry other than said one or more memory cells is powered via a first supply voltage generated by said power supply;
said one or more memory cells are powered via a second supply voltage generated by said power supply;
said power supply is operable to:
control said first supply voltage independent of said second supply voltage; and
adjust said second supply voltage based on a type of data stored in said one or more memory cells;
each of said one or more memory cells comprises cross-coupled inverters;
said one or more memory cells are a first one or more memory cells;
said system also comprises a second one or more memory cells powered via a third supply voltage generated by said power supply;
said first one or more memory cells hold a corresponding one or more most significant bits of a data word; and said second one or more memory cells hold a corresponding one or more least significant bits of said data word.
72. The system of claim 71 , wherein cell size of said first one or more memory cells is the same as cell size of said second one or more memory cells.
73. The system of claim 72 , wherein said second supply voltage is higher than said third supply voltage.
74. The system of claim 71 , wherein cell size of said first one or more memory cells is larger than cell size of said second one or more memory cells.
75. The system of claim 74 , wherein said second supply voltage is equal to said third supply voltage.
76. A system comprising:
an electronic device comprising a power supply, one or more memory cells, and digital circuitry other than said one or more memory cells, wherein:
said digital circuitry other than said one or more memory cells is powered via a first supply voltage generated by said power supply;
said one or more memory cells are powered via a second supply voltage generated by said power supply;
said power supply is operable to:
control said first supply voltage independent of said second supply voltage; and
adjust said second supply voltage based on a type of data stored in said one or more memory cells;
each of said one or more memory cells comprises cross-coupled inverters;
said one or more memory cells are a first one or more memory cells;
said system also comprises a second one or more memory cells powered via a third supply voltage generated by said power supply;
said first one or more memory cells hold a corresponding one or more bits of a data word having a first fault sensitivity coefficient; and
said second one or more memory cells hold a corresponding one or more bits of said data word having a second fault sensitivity coefficient.
77. The system of claim 76 , wherein cell size of said first one or more memory cells is the same as cell size of said second one or more memory cells.
78. The system of claim 77 , wherein said second supply voltage is higher than said third supply voltage.
79. The system of claim 76 , wherein cell size of said first one or more memory cells is larger than cell size of said second one or more memory cells.
80. A system comprising:
an electronic device comprising a power supply, one or more memory cells, and digital circuitry other than said one or more memory cells, wherein:
said digital circuitry other than said one or more memory cells is powered via a first supply voltage generated by said power supply;
said one or more memory cells are powered via a second supply voltage generated by said power supply;
said power supply is operable to:
control said first supply voltage independent of said second supply voltage; and
adjust said second supply voltage based on a type of data stored in said one or more memory cells;
each of said one or more memory cells comprises cross-coupled inverters;
said one or more memory cells are a first one or more memory cells;
said system also comprises a second one or more memory cells powered via a third supply voltage generated by said power supply; and
said second supply voltage is equal to said third supply voltage.
81. A system comprising:
an electronic device comprising a power supply, one or more memory cells, and digital circuitry other than said one or more memory cells, wherein:
said digital circuitry other than said one or more memory cells is powered via a first supply voltage generated by said power supply;
said one or more memory cells are powered via a second supply voltage generated by said power supply;
said power supply is operable to:
control said first supply voltage independent of said second supply voltage; and
adjust said second supply voltage based on a type of data stored in said one or more memory cells;
each of said one or more memory cells comprises cross-coupled inverters; and
said adjustment results in said second supply voltage being a first voltage when a first type of data is stored in said one or more memory cells and said second supply voltage being a second voltage when a second type of data is stored in said one or more memory cells.
82. A system comprising:
an electronic device comprising a power supply, one or more memory cells, and digital circuitry other than said one or more memory cells, wherein:
said digital circuitry other than said one or more memory cells is powered via a first supply voltage generated by said power supply;
said one or more memory cells are powered via a second supply voltage generated by said power supply;
said power supply is operable to:
control said first supply voltage independent of said second supply voltage; and
adjust said second supply voltage based on a type of data stored in said one or more memory cells;
each of said one or more memory cells comprises cross-coupled inverters; and
said second supply voltage is applied to a source node of one or more access transistors that provide power to said one or more memory cells.