IP Library Granted Patent US 9,300,255
Granted Patent B2
US 9,300,255 · App. 14/451,288 · Granted Mar 29, 2016

Radio communication circuit and radio communication apparatus

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Quick Facts
Patent No.
US 9,300,255
App. No.
14/451,288
Granted
Mar 29, 2016
Kind
B2
Abstract

A radio communication circuit includes a power amplifier configured to amplify a signal and output the amplified signal, an envelope detector configured to extract an envelope of an input signal inputted to the power amplifier, an offset generator configured to generate an offset value for a power supply voltage to be applied to the power amplifier, based on a distortion amount in an output signal from the power amplifier, and a power supply voltage modulator configured to control the power supply voltage to be applied to the power amplifier based on the envelope extracted and the offset value generated.

Claims (25)

1. A radio communication circuit comprising:

a power amplifier configured to amplify a signal and output the amplified signal;

an envelope detector configured to extract an envelope of an input signal inputted to the power amplifier;

an offset generator configured to generate an offset value for a power supply voltage to be applied to the power amplifier, based on a distortion amount in an output signal from the power amplifier; and

a power supply voltage modulator configured to control the power supply voltage to be applied to the power amplifier based on the envelope extracted and the offset value generated,

wherein the distortion amount in the output signal from the power amplifier is expressed as a ratio between first power of the output signal from the power amplifier and second power of a signal on a channel adjacent to a channel for the output signal from the power amplifier.

2. The radio communication circuit according to claim 1 , wherein the offset generator includes a quadrature demodulator configured to perform a quadrature demodulation on the amplified signal and a distortion judgment circuit configured to detect the distortion amount from an output of the quadrature demodulator.

3. The radio communication circuit according to claim 1 , wherein the offset value is expressed as a value proportional to a difference between the distortion amount in the output signal from the power amplifier and a preset target distortion amount.

4. The radio communication circuit according to claim 3 , further comprising:

a memory that stores a table including the offset value associated with the difference between the distortion amount in the output signal from the power amplifier and the preset target distortion amount.

5. The radio communication circuit according to claim 1 , further comprising:

a filter configured to extract the signal on the channel adjacent to the channel for the output signal from the power amplifier.

6. A radio communication apparatus comprising:

a radio communication circuit configured to amplify a signal by a power amplifier, extract an envelope of an input signal inputted to the power amplifier, generate an offset value for a power supply voltage to be applied to the power amplifier, based on a distortion amount in an output signal from the power amplifier, and control the power supply voltage to be applied to the power amplifier based on the extracted envelope and the generated offset value; and

an antenna coupled to the radio communication circuit and configured to transmit the amplified signal,

wherein the distortion amount in the output signal from the power amplifier is expressed as a ratio between power of the output signal from the power amplifier and power of a signal on a channel adjacent to a channel for the output signal from the power amplifier.

7. The radio communication circuit according to claim 2 , wherein the distortion judgment circuit includes a first level detection circuit configured to detect a power level of an output of the quadrature demodulator as the first power and a second level detection circuit configured to detect a power level of an output of a filter which receives the output of the quadrature demodulator as the second power.

8. The radio communication circuit according to claim 7 , wherein the distortion judgment circuit includes a level ratio calculation circuit calculates the ratio of the power level detected by the first level detection circuit to the power level detected by the second level detection circuit.

9. The radio communication apparatus according to claim 6 , wherein the offset value is expressed as a value proportional to a difference between the distortion amount in the output signal from the power amplifier and a preset target distortion amount.

10. The radio communication apparatus according to claim 9 , further comprising:

a memory that stores a table including the offset value associated with the difference between the distortion amount in the output signal from the power amplifier and the preset target distortion amount.

11. The radio communication apparatus according to claim 6 , wherein the radio communication circuit includes a filter configured to extract the signal on the channel adjacent to the channel for the output signal from the power amplifier.

12. The radio communication apparatus according to claim 6 , wherein the radio communication circuit includes a quadrature demodulator configured to perform a quadrature demodulation on an amplified signal from the power amplifier and a distortion judgment circuit configured to detect the distortion amount from an output of the quadrature demodulator.

13. The radio communication apparatus according to claim 12 , wherein the distortion judgment circuit includes a first level detection circuit configured to detect a power level of an output of the quadrature demodulator as the first power and a second level detection circuit configured to detect a power level of an output of a filter which receives the output of the quadrature demodulator as the second power.

14. The radio communication apparatus according to claim 13 , wherein the distortion judgment circuit includes a level ratio calculation circuit calculates the ratio of the power level detected by the first level detection circuit to the power level detected by the second level detection circuit.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2024
From: YAMATO KANZAI LIMITED
To: FCNT LLC
Reel/Frame 066908/0856 →
CHANGE OF NAME Recorded Mar 21, 2024
From: FCNT LIMITED
To: YAMATO KANZAI LIMITED
Reel/Frame 066854/0942 →
CHANGE OF NAME Recorded Mar 19, 2024
From: FUJITSU CONNECTED TECHNOLOGIES LIMITED
To: FCNT LIMITED
Reel/Frame 066832/0399 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2018
From: FUJITSU LIMITED
To: FUJITSU CONNECTED TECHNOLOGIES LIMITED
Reel/Frame 047577/0943 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2014
From: TAKEUCHI, YASUAKI; YAMAMORI, YUSUKE; MURAKAMI, YASUHIRO; TANII, TAKASHI; HAYASHIHARA, MIKIO
To: FUJITSU LIMITED
Reel/Frame 033459/0097 →