Satellite signal frequency translation and stacking
View Patent ↗An outdoor satellite receiving unit (ODU) receives several independent satellite signals, selects two signals with a switch matrix, downconverts the two signals to a bandstacked signal with a high and a low band signal, and outputs the bandstacked signal on the same cable to receiver units. Several satellite signals can be selected in groups of two or more and output to independent receiver units. Signal selecting is performed at the received radio frequency (RF) and bandstacking is performed with a single downconversion step to an intermediate frequency (IF). Channel stacking on the same cable of more than two channels from several satellites can be achieved by using frequency agile downconverters and bandpass filters prior to combining at the IF output. A slow transitioning switch minimizes signal disturbances when switching and maintains input impedance at a constant value.
1. A system comprising:
an input port;
an output port;
an internal termination having an impedance of Z;
a first switch component having first variable impedance Z 1 coupled between the input port and the internal termination; and
a second switch component having second variable impedance Z 2 coupled between the input port and the output port; and
a switch control circuit for control of the impedance of both the first switch component and the second switch component to maintain a substantially constant input impedance when the system is any state, including ON, OFF, and in transition, wherein:
the switch control circuit is configured to generate a time varying control signal having a controllable rate of change to control the impedances Z 1 and Z 2 at a given time;
the impedance relationship substantially achieved by the switch control circuit is described by the equation Z 1 ·Z 2 =Z 2 ;
the substantially constant input impedance has an impedance of Z;
the switch control circuitry is configured to linearly change the impedance Z 1 with time when the system is in transition; and
the switch control circuitry is configured to hyperbolically change the impedance Z 2 with time when the system is in transition.
2. The system of claim 1 , wherein the first switch component is a field-effect transistor (FET) switch and wherein the second switch component is a second FET switch.
3. The system of claim 2 , wherein the switch control circuit comprises:
a first digital to analog converter (DAC) coupled to the first FET switch and configured to generate a voltage to control the impedance Z1 of the first FET switch as a function of time; and
a second DAC coupled to the second FET switch and configured to generate a voltage to control the impedance Z3 of the second FET switch as a function of time.
4. The system of claim 3 , wherein the switch control circuit comprises a linearized transconductance circuit driven by differential sweep signals when the switch element transitions, wherein the differential sweep signals generate complementary control voltages VDCM and VDCP configured to drive the first FET switch and the second FET switch, respectively.
5. A system comprising:
a switch element, comprising: an input port;
an output port;
an internal termination having an impedance Z;
a first switch component having first variable impedance Z± coupled between the input port and the internal termination; and
a second switch component having second variable impedance Zz coupled between the input port and the output port;
a switch control circuit for control of the impedance of both the first switch component and the second switch component to maintain a substantially constant input impedance when the switch element is any state, including ON, OFF, and in transition, wherein;
the switch control circuit is configured to generate a time varying control signal having a controllable rate of change to control the impedances Z1 and Z2 at a given time;
the impedance relationship substantially achieved by the switch control circuit is described by the equation Z1*Z2=Z^2;
the substantially constant input impedance has an impedance of Z;
the switch control circuit is configured to hyperbolically change linearly change the impedance Z2 with time when the switch element is in transition.
6. The system of claim 5 , wherein the switch element is a single pole double throw (SPDT) switch element.
7. The system of claim 5 , wherein the first switch component is a first field-effect transistor (FET) switch and wherein the second switch component is a second FET switch.
8. The system of claim 7 , wherein the switch control circuit comprises:
a first digital to analog converter (DAC) coupled to the first FET switch and configured to generate a voltage to control the impedance Z 1 of the first FET switch as a function of time; and
a second DAC coupled to the second FET switch and configured to generate a voltage to control the impedance Z 2 of the second FET switch as a function of time.
9. The system of claim 7 , wherein the switch control circuit comprises a linearized transconductance circuit driven by differential sweep signals when the switch element transitions, wherein the differential sweep signals generate complementary control voltages VDCM and VDCP configured to drive the first FET switch and the second FET switch, respectively.
10. A system comprising:
a switch element, comprising: an input port;
an output port; an internal termination having an impedance Z;
a first switch component having first variable impedance Z1 coupled between the input port and the internal termination; and
a second switch component having second variable impedance Z2 coupled between the input port and the output port;
a switch control circuit for control of the impedance of both the first switch component and the second switch component to maintain a substantially constant input impedance when the switch element is any state, including ON, OFF, and in transition, wherein:
the switch control circuit is configured to generate a time varying control signal having a controllable rate of change to control the impedances Z1 and Z2 at a given time; the impedance relationship substantially achieved by the switch control circuit is described by the equation Z1*Z2=Z^2;
wherein the substantially constant input impedance has an impedance of Z;
the first switch component is a first field-effect transistor (FET) switch;
the second switch component is a second FET switch; and the switch control circuit comprises:
a first digital to analog converter (DAC) coupled to the first FET switch and configured to generate a voltage to control the impedance Z1 of the first FET switch as a function of time; and
a second DAC coupled to the second FET switch and configured to generate a voltage to control the impedance Z2 of the second FET switch as a function of time.
11. The system of claim 10 , wherein the switch element is a single pole double throw (SPDT) switch element.
12. The system of claim 10 , wherein the switch control circuit is configured to linearly change the impedance Z 1 with time when the switch element is in transition.
13. A system comprising: a switch element, comprising:
an input port;
an output port; an internal termination having an impedance Z;
a first switch component having first variable impedance Z1 coupled between the input port and the internal termination; and
a second switch component having second variable impedance Z2 coupled between the input port and the output port;
a switch control circuit for control of the impedance of both the first switch component and the second switch component to maintain a substantially constant input impedance when the switch element is any state, including ON, OFF, and in transition, wherein:
the switch control circuit generates a time varying control signal having a controllable rate of change to control the impedances Z1 and Z2 at a given time;
the impedance relationship substantially achieved by the switch control circuit is described by the equation Z1*Z2=Z^2;
the substantially constant input impedance has an impedance of Z;
the first switch component is a first field-effect transistor (FET) switch;
the second switch component is a second FET switch; and
the switch control circuit comprises a linearized transconductance circuit driven by differential sweep signals when the switch element transitions, wherein the differential sweep signals generate complementary control voltages VDCM and VDCP configured to drive the first FET switch and the second FET switch, respectively.
14. The system of claim 10 , wherein the switch element is a single pole double throw (SPDT) switch element.
15. The system of claim 10 , wherein the switch control circuit is configured to linearly change the impedance Z 1 with time when the switch element is in transition.
16. A system comprising:
an input port;
an output port;
an internal termination having an impedance of Z;
a first switch component having first variable impedance Z 1 coupled between the input port and the internal termination; and
a second switch component having second variable impedance Z 2 coupled between the input port and the output port; and
a switch control circuit for control of the impedance of both the first switch component and the second switch component to maintain a substantially constant input impedance when the system is any state, including ON, OFF, and in transition, wherein:
the switch control circuit generates a time varying control signal having a controllable rate of change to control the impedances Z 1 and Z 2 at a given time;
the impedance relationship substantially achieved by the switch control circuit is described by the equation Z 1 ·Z 2 =Z 2 ;
the substantially constant input impedance has an impedance of Z;
the first switch component is a first field-effect transistor (FET) switch;
the second switch component is a second FET switch; and
the switch control circuit comprises:
a first digital to analog converter (DAC) coupled to the first FET switch and configured to generate a voltage to control the impedance Z1 of the first FET switch as a function of time; and
a second DAC coupled to the second FET switch and configured to generate a voltage to control the impedance Z3 of the second FET switch as a function of time.
17. The system of claim 16 , wherein the switch control circuitry is configured to linearly change the impedance Z 1 with time when the system is in transition.
18. A system comprising:
an input port;
an output port;
an internal termination having an impedance of Z;
a first switch component having first variable impedance Z 1 coupled between the input port and the internal termination; and
a second switch component having second variable impedance Z 2 coupled between the input port and the output port; and
a switch control circuit for control of the impedance of both the first switch component and the second switch component to maintain a substantially constant input impedance when the system is any state, including ON, OFF, and in transition, wherein:
the switch control circuit generates a time varying control signal having a controllable rate of change to control the impedances Z 1 and Z 2 at a given time;
the impedance relationship substantially achieved by the switch control circuit is described by the equation Z 1 ·Z 2 =Z 2 ;
the substantially constant input impedance has an impedance of Z;
the first switch component is a first field-effect transistor (FET) switch;
the second switch component is a second FET switch; and
the switch control circuit comprises a linearized transconductance circuit driven by differential sweep signals when the switch element transitions, wherein the differential sweep signals generate complementary control voltages VDCM and VDCP configured to drive the first FET switch and the second FET switch, respectively.
19. The system of claim 18 , wherein the switch control circuitry is configured to linearly change the impedance Z 1 with time when the system is in transition.