IP Library Granted Patent US 9,292,440
Granted Patent B2
US 9,292,440 · App. 14/451,687 · Granted Mar 22, 2016

Adaptive over-provisioning in memory systems

Inventors: Ofir Shalvi (Ra'anana, IL); Naftali Sommer (Rishon Le-Zion, IL); Yoav Kasorla (Kfar Netar, IL)
Assignee: Apple Inc.
G06F12/0802G06F3/0619G06F3/0665G06F3/0688G06F11/10G06F11/1008G06F12/02G06F12/023G06F12/0246G06F3/061G06F12/0223G06F2212/7205Y02B60/1225
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Quick Facts
Patent No.
US 9,292,440
App. No.
14/451,687
Granted
Mar 22, 2016
Kind
B2
Abstract

A method for data storage includes, in a memory that includes multiple memory blocks, specifying at a first time a first over-provisioning overhead, and storing data in the memory while retaining in the memory blocks memory areas, which do not hold valid data and whose aggregated size is at least commensurate with the specified first over-provisioning overhead. Portions of the data from one or more previously-programmed memory blocks containing one or more of the retained memory areas are compacted. At a second time subsequent to the first time, a second over-provisioning overhead, different from the first over-provisioning overhead, is specified, and data storage and data portion compaction is continued while complying with the second over-provisioning overhead.

Claims (37)

1. An apparatus, comprising:

a cache memory;

a long-term storage unit; and

a controller configured to:

receive data from a host for storage;

store the data in a portion of the cache memory allocated to the host, wherein a size of the portion of the cache memory is dependent upon an over-provisioning ratio;

store the data in the long-term storage unit;

modify the over-provisioning ratio dependent upon a storage throughput of a storage system including the cache memory and the long-term storage unit.

2. The apparatus of claim 1 , wherein to modify the over-provisioning ratio, the controller is further configured to modify a map between logical addresses and physical storage locations in the cache memory.

3. The apparatus of claim 1 , wherein the cache memory comprises a solid-state disk.

4. The apparatus of claim 1 , wherein the controller is further configured to receive a trim command from the host.

5. The apparatus of claim 1 , wherein to modify the over-provisioning ratio, the controller is further configured to delete one or more data items from the cache memory.

6. The apparatus of claim 1 , wherein to modify the over-provisioning ratio, the controller is further configured to modify a level of redundancy of data stored in the cache memory.

7. A method, comprising:

receiving data from a host for storage;

storing the data in a portion of a cache memory allocated to the host, wherein a size of the portion of the cache memory is dependent upon an over-provisioning ratio;

storing the data in a long-term storage unit; and

modifying the over-provisioning ratio dependent upon a storage throughput of a storage system including the cache memory and the long-term storage unit.

8. The method of claim 7 , wherein modifying the over-provisioning ratio comprises modifying a map between logical addresses and physical storage locations in the cache memory.

9. The method of claim 7 , further comprising receiving a trim command from the host.

10. The method of claim 7 , wherein modifying the over-provisioning ratio comprises deleting one or more data items from the cache memory.

11. The method of claim 7 , wherein modifying the over-provisioning ratio comprises modifying a level of redundancy of data stored in the cache memory.

12. The method of claim 7 , wherein the cache memory includes a plurality of memory cells, and wherein increasing the over-provisioning ratio comprises modifying a number of bits stored in a given memory cell of the plurality of memory cells.

13. The method of claim 7 , wherein the cache memory comprises a solid-state disk.

14. A system, comprising:

a storage unit; and

a host processor configured to send data to the storage unit;

wherein the storage unit includes a cache memory, and wherein the storage unit is configured to:

receive the data from the host processor;

store the data in a portion of the cache memory allocated to the host processor, wherein a size of the portion is dependent upon an over-provisioning ratio; and

modify the over-provisioning ratio dependent upon a storage throughput of the storage unit.

15. The system of claim 14 , wherein to modify the over-provisioning ratio, the storage unit is further configured to modify a map between logical addresses and physical storage locations in the cache memory.

16. The system of claim 14 , wherein to modify the over-provisioning ratio, the storage unit is further configured to delete one or more data items from the cache memory.

17. The system of claim 14 , wherein to modify the over-provisioning ratio, the storage unit is further configured to modify a level of redundancy of data stored in the cache memory.

18. The system of claim 14 , wherein the cache memory includes a plurality of memory cells, and wherein to increase the over-provisioning ratio, the storage unit is further configured to modify a number of bits stored in a given memory cell of the plurality of memory cells.

19. The system of claim 14 , wherein the storage unit is further configured to receive a trim command from the host processor.

20. The system of claim 16 , wherein to delete the one or more data items from the cache memory, the storage unit is further configured to select at least one least-accessed data item.

Continuity (7)
Continuation 14150212 · Jan 8, 2014
Continuation 13908018 · Jun 3, 2013
Continuation 12822207 · Jun 24, 2010
Provisional Application 61224897 · Jul 12, 2009
Provisional Application 61293814 · Jan 11, 2010
Provisional Application 61334606 · May 14, 2010
Related Publication 20140344524A1 · Nov 20, 2014