IP Library Granted Patent US 9,064,775
Granted Patent B2
US 9,064,775 · App. 14/452,203 · Granted Jun 23, 2015

Gallium nitride semiconductor structures with compositionally-graded transition layer

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Quick Facts
Patent No.
US 9,064,775
App. No.
14/452,203
Granted
Jun 23, 2015
Kind
B2
Abstract

The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

Claims (25)

1. A semiconductor structure comprising:

a transition layer comprising an alloy of gallium nitride consisting of Al x In y Ga (1-x-y) N;

a gallium nitride layer over said transition layer;

wherein said transition layer is discontinuously graded.

2. The semiconductor structure of claim 1 , wherein a value of y of said transition layer is selected from the group consisting of zero and substantially zero.

3. The semiconductor structure of claim 1 , wherein said discontinuously graded transition layer is step-wise graded.

4. The semiconductor structure of claim 1 , wherein a value of 1-x-y at a front surface of said transition layer is greater than a value of 1-x-y at a back surface of said transition layer.

5. The semiconductor structure of claim 1 , wherein a composition of said gallium nitride layer at a bottom surface thereof is different from a composition of said transition layer at a front surface thereof.

6. The semiconductor structure of claim 1 , wherein a gallium percentage in said gallium nitride layer at a bottom surface thereof is different from a gallium percentage of said transition layer at a front surface thereof.

7. The semiconductor structure of claim 1 , wherein a value of x+y of said transition layer at a front surface thereof is less than 0.3.

8. The semiconductor structure of claim 1 , wherein a thickness of said gallium nitride layer is greater than 0.1 microns.

9. The semiconductor structure of claim 1 , wherein a thickness of said gallium nitride layer is greater than 2.0 microns.

10. The semiconductor structure of claim 1 , wherein said transition layer is situated over a substrate.

11. The semiconductor structure of claim 1 , wherein said transition layer is situated over a silicon substrate.

12. The semiconductor structure of claim 1 , wherein said transition layer is situated over an intermediate layer.

13. The semiconductor structure of claim 1 , wherein said transition layer is situated above an intermediate layer comprising an alloy of gallium nitride consisting of Al x In y Ga (1-x-y) N.

14. The semiconductor structure of claim 13 , wherein a value of x+y of said intermediate layer is greater than 0.4.

15. The semiconductor structure of claim 13 , wherein a value of x+y of said intermediate layer is different from a value of 1-x-y of said transition layer at a back surface thereof.

16. The semiconductor structure of claim 1 , wherein said semiconductor structure is part of a FET.

17. The semiconductor structure of claim 1 , wherein said semiconductor structure is part of an LED.

18. A method for forming a semiconductor structure, said method comprising:

forming a discontinuously graded transition layer comprising an alloy of gallium nitride consisting of Al x In y Ga (1-x-y) N;

forming a gallium nitride layer over said transition layer.

19. The method of claim 18 , wherein a value of y of said transition layer is selected from the group consisting of zero and substantially zero.

20. The method of claim 18 , wherein a value of 1-x-y at a front surface of said transition layer is greater than a value of 1-x-y at a back surface of said transition layer.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2019
From: INFINEON TECHNOLOGIES AMERICAS CORP.
To: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
Reel/Frame 047907/0629 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2018
From: NITRONEX CORPORATION
To: INTERNATIONAL RECTIFIER CORPORATION
Reel/Frame 047836/0166 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY NAME PREVIOUSLY RECORDED AT REEL: 33469 FRAME: 152. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 17, 2018
From: WEEKS, T. WARREN, JR.; PINER, EDWIN L.; GEHRKE, THOMAS; LINTHICUM, KEVIN J.
To: NITRONEX CORPORATION
Reel/Frame 048311/0027 →
CONFIDENTIAL EXCLUSIVE LICENSE AND IP PURCHASE AGREEMENTS THAT RESTRICT PATENT ASSIGNMENT BY CURRENT OWNER (ONLY NON-CONFIDENTIAL, PUBLIC MATERIALS SUMMARIZING AGREEMENTS AND LITIGATION DISPUTES RELATING TO THE SAME ATTACHED) Recorded Nov 3, 2017
From: INTERNATIONAL RECTIFIER CORPORATION
To: NITRONEX LLC; MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
Reel/Frame 044532/0627 →
MERGER AND CHANGE OF NAME Recorded Mar 18, 2016
From: INTERNATIONAL RECTIFIER CORPORATION; INFINEON TECHNOLOGIES AMERICAS CORP.
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 038036/0943 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2014
From: WEEKS, T. WARREN, JR.; PINER, EDWIN L.; GEHRKE, THOMAS; LINTHICUM, KEVIN J.
To: INTERNATIONAL RECTIFIER CORPORATION
Reel/Frame 033469/0152 →