CMOS interpolator for a serializer/deserializer communication application
View Patent ↗A phase interpolator (PI) is provided to adjust the phase of a clock such that the phase is aligned to an incoming data pattern from a data stream. The data can be captured from a device such as a flip-flop or the like. The present technique uses a PI (digital to phase) and a digital state machine in a feedback loop to set the correct digital code to the PI inputs to achieve an appropriate clock phase. Of course, there can be variations.
1. An integrated transceiver circuit device comprising:
a plurality of receivers coupled to a plurality of channels, each of the channels being configured for transmitting asynchronous data to one of the receivers, each of the receivers comprising:
a pre-amplifier device having an input and an output, the input being coupled to a channel associated with the receiver; and
a comparator device comprising an input coupled to the pre-amplifier, and configured to identify one or more binary states; and
a PLL device, the PLL device being common to and being coupled to each receivers;
a phase interpolator device coupled to the PLL device and is configured to perform a digital to phase conversion; and
a timing recovery loop module being configured to generate a driving signal for driving the phase interpolator device.
2. The device of claim 1 wherein the phase interpolator device is characterized using a CMOS interpolation that is linear.
3. The device of claim 1 wherein the plurality of receivers are coupled to a SerDes device, and coupled to a plurality of transmitters.
4. The device of claim 1 wherein the phase interpolator device is characterized by a phase linearity and a dynamic performance.
5. The device of claim 1 wherein the phase interpolator device comprises a pair of mixers configured to mix a first clock and a second clock spaced by 90 Degrees from each other.
6. The device of claim 1 wherein the phase interpolator device comprises a first PI core and a second PI core coupled to the first PI core.
7. The device of claim 1 wherein the phase interpolator device is configured with a thermal setting.
8. The device of claim 1 wherein the phase interpolator device comprises a first PI core and a second PI core coupled to the first PI core, each of the first PI core and the second PI core being characterized by a resetting characteristic by a reset pulse during a conclusion of a mixing operation.