Encoding and Decoding Schemes to Achieve Standard Compliant Mean Time to False Packet Acceptance
Systems and methods for enabling encoding/decoding schemes that satisfy the IEEE 802.3 Mean Time To False Packet Acceptance (MTTFPA) requirement in an Ethernet Passive Optical Network over Coax (EPoC) are described. The proposed encoding/decoding schemes assume existing Medium Access Control (MAC) layer Cyclic Redundancy Check (CRC) encoding/decoding, thereby requiring no changes in the Ethernet Passive Optical Network (EPON) MAC protocol, but increase error protection in the EPoC physical layer (PHY) to meet the MTTFPA requirement without sacrificing desired Ethernet frame loss ratios and downstream/upstream data rates for EPoC.
1 . A physical layer (PHY) device, comprising:
interface circuitry configured to receive a stream of MAC frames from a Medium Access Control (MAC) layer module; and
processing circuitry configured to:
form a plurality of data blocks from the stream of MAC frames;
compute a Cyclic Redundancy Check (CRC) bit sequence based on the plurality of data blocks;
append the CRC bit sequence to the plurality of data blocks to form a Forward Error Correction (FEC) payload; and
encode the FEC payload using an FEC code to generate an FEC codeword.
2 . The PHY device of claim 1 , wherein the MAC frames include Ethernet Passive Optical Network (EPON) frames.
3 . The PHY device of claim 1 , wherein the processing circuitry is further configured to:
generate a plurality of first data blocks from the stream of MAC frames;
line encode each of the plurality of first data blocks to generate a respective plurality of line encoded data blocks; and
shorten a synchronization header of each of the plurality of line encoded data blocks to generate the plurality of data blocks.
4 . The PHY device of claim 3 , wherein each of the plurality of first data blocks is J bits long, and wherein the processing circuitry is configured to line encode each of the plurality of first data blocks using a line code of rate J/(K+L).
5 . The PHY device of claim 4 , wherein the synchronization header of each of the plurality of line encoded data blocks is (K+L−J) bits long.
6 . The PHY device of claim 5 , wherein the shortened synchronization header of each of the plurality of line encoded data blocks is L−J bits, and wherein each of the plurality of data blocks is L bits long.
7 . The PHY device of claim 1 , wherein a generator polynomial of the CRC bit sequence is equal to x 40 +x 26 +x 23 +x 17 +x 3 +1.
8 . The PHY device of claim 1 , wherein the CRC bit sequence is at least 36 bits long.
9 . The PHY device of claim 1 , wherein the CRC bit sequence is 40 bits long.
10 . The PHY device of claim 1 , wherein the FEC code is a soft decision code.
11 . The PHY device of claim 10 , wherein the FEC code is a Low Density Parity Check (LDPC) code.
12 . The PHY device of claim 1 , wherein the processing circuitry is further configured to transmit the FEC codeword over an Ethernet Passive Optical Network over Coax (EPoC) to a second PHY device.
13 . A method, comprising:
receiving a stream of MAC frames from a Medium Access Control (MAC) layer;
forming a plurality of data blocks from the stream of MAC frames;
computing a Cyclic Redundancy Check (CRC) bit sequence based on the plurality of data blocks;
appending the CRC bit sequence to the plurality of data blocks to form a Forward Error Correction (FEC) payload; and
encoding the FEC payload using an FEC code to generate an FEC codeword.
14 . The method of claim 13 , wherein a generator polynomial of the CRC bit sequence is equal to x 40 +x 26 +x 23 +x 17 +x 3 +1.
15 . The method of claim 13 , wherein the CRC bit sequence is at least 36 bits long.
16 . The method of claim 13 , wherein the FEC code is a Low Density Parity Check (LDPC) code.
17 . A physical layer (PHY) device, comprising:
processing circuitry configured to:
receive a Forward Error Correction (FEC) codeword;
decode the FEC codeword using an FEC code to generate an FEC payload, the FEC payload comprising a plurality of data blocks and a first Cyclic Redundancy Check (CRC) bit sequence;
compute a second CRC bit sequence based on the plurality of data blocks; and
compare the first CRC bit sequence with the second CRC bit sequence; and
interface circuitry configured to:
forward all of the plurality of data blocks to a Medium Access Control (MAC) layer module when the first CRC bit sequence is equal to the second CRC bit sequence; and
discard a subset of the plurality of data blocks when the first CRC bit sequence is not equal to the second CRC bit sequence.
18 . The PHY device of claim 17 , wherein when the first CRC bit sequence is not equal to the second CRC bit sequence, the processing circuitry is configured to mark the subset of the plurality of data blocks with an error indication.
19 . The PHY device of claim 18 , wherein the plurality of data blocks include a plurality of MAC frames, and wherein the processing circuitry is configured to select the subset of the plurality of data blocks such that discarding the subset causes an error in each of the plurality of MAC frames.
20 . The PHY device of claim 18 , wherein the plurality of data blocks are line encoded, and wherein when the first CRC bit sequence is not equal to the second CRC bit sequence, the processing circuitry is configured to attach an invalid line encoding synchronization header to each data block of the subset of the plurality of data blocks.