IP Library Granted Patent US 10,416,109
Granted Patent B2
US 10,416,109 · App. 14/454,659 · Granted Sep 17, 2019

Microchip structure and treatments for electrochemical detection

Inventors: Graham D. Jack (Toronto, CA); Ryan B. Hayman (Toronto, CA)
Assignee: General Atomics
G01N27/327B81B1/006B81C1/00206B81C1/00341
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Quick Facts
Patent No.
US 10,416,109
App. No.
14/454,659
Granted
Sep 17, 2019
Kind
B2
Abstract

Disclosed herein are processes and devices for use in the electrochemical detection of a target in a sample. For example, silicon or glass surfaces are treated with silanes functionalized with various side chains to tune the surface wetting characteristics.

Claims (31)

1. A process for the manufacture of a biosensing device, the process comprising:

providing a substrate having an electrically conductive lead on a surface thereof;

applying an insulating layer to the substrate and the electrically conductive lead, said insulating layer comprising one or more of silicon dioxide and silicon nitride;

etching an aperture in the insulating layer to expose a portion of the electrically conductive lead onto which a nanostructured microelectrode is to be plated;

oxidizing one or more of the silicon dioxide and the silicon nitride to form oxidized silicon dioxide or oxidized silicon nitride;

allowing one or more of the oxidized silicon dioxide and the oxidized silicon nitride to react with a functionalized silane; and

forming a self-assembled monolayer of the functionalized silane on the insulating layer.

2. The process of claim 1 , wherein the insulating layer comprises a layer of silicon dioxide and a layer of silicon nitride.

3. The process of claim 2 , wherein the layer of silicon dioxide is disposed between the substrate and the layer of silicon nitride.

4. The process of claim 1 , wherein the step of oxidizing one or more of the silicon dioxide and the silicon nitride occurs at a top surface of the insulating layer.

5. The process of claim 1 , wherein the step of oxidizing one or more of the silicon dioxide and the silicon nitride forms a deactivated oxidized silicon dioxide or a deactivated oxidized silicon nitride.

6. The process of claim 1 , wherein a plurality of insulating layers is applied to the substrate.

7. The process of claim 1 , wherein the aperture is etched through the insulating layer.

8. The process of claim 1 , wherein allowing one or more of the oxidized silicon dioxide and the oxidized silicon nitride to react with the functionalized silane includes applying a vacuum.

9. The process of claim 1 , wherein the self-assembled monolayer of a functionalized silane provides a hydrophobic coating.

10. A process for the manufacture of a biosensing device, the process comprising:

providing a substrate having an electrically conductive lead on a surface thereof;

applying an insulating layer to the substrate and the electrically conductive lead, said insulating layer comprising one or more of silicon dioxide and silicon nitride;

etching an aperture in the insulating layer to expose a portion of the electrically conductive lead onto which a nanostructured microelectrode is to be plated;

etching a surface of the insulating layer and a surface of the electrically conductive lead to clean and/or oxidize the surfaces; and

capping the etched surface of the insulating layer with a self-assembled monolayer of functionalized silane.

11. The process of claim 10 , wherein a plurality of insulating layers is applied to the substrate.

12. The process of claim 11 , wherein the aperture is etched through an insulating layer.

13. The process of claim 10 , wherein etching the surface comprises subjecting the surface to plasma etching.

14. The process of claim 10 , wherein the functionalized silane is a trichlorosilane.

15. The process of claim 14 , wherein the trichlorosilane has a functionalized alkyl side chain.

16. The process of claim 15 , wherein the trichlorosilane is trichloro(1H, 1H, 2H, 2H-perfluorooctyl) silane or trichlorododecylsilane.

17. The process of claim 10 , wherein oxidizing the surface occurs during exposure to oxygen plasma.

18. The process of claim 10 , further comprising: plating the nanostructured microelectrode in the aperture.

19. The process of claim 10 , wherein capping the etched surface of the insulating layer with the self-assembled monolayer of functionalized silane includes reacting the functionalized silane under a vacuum with an oxidized surface of the insulating layer.

20. The process of claim 10 , wherein the self-assembled monolayer of a functionalized silane provides a hydrophobic coating.

Assignments (3)
SECURITY INTEREST Recorded Apr 10, 2020
From: GENERAL ATOMICS
To: BANK OF THE WEST
Reel/Frame 052372/0067 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2018
From: A. FARBER & PARTNERS INC., AS COURT-APPOINTED RECEIVER FOR XAGENIC INC.
To: GENERAL ATOMICS
Reel/Frame 045067/0529 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 12, 2014
From: JACK, GRAHAM D.; HAYMAN, RYAN B.
To: XAGENIC INC.
Reel/Frame 033513/0027 →
Continuity (2)
Provisional Application 61863398 · Aug 7, 2013
Related Publication 20150041315A1 · Feb 12, 2015